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Chapter 8:

Chapter 8:. 4343 - Computer Organization & Design. Central Processing Unit. ALU. CPU. CU. Register File. General Register Organization. Input. R1. R2. R3. R4. R5. R6. R7. MUX. MUX. LD. SEL A. SEL B. 3 x 8 Decoder. A. B. OPR. ALU. SEL D. Input. R1. R2. R3. R4. R5.

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Chapter 8:

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  1. Chapter 8: 4343 - Computer Organization & Design Central Processing Unit

  2. ALU CPU CU Register File

  3. General Register Organization Input R1 R2 R3 R4 R5 R6 R7 MUX MUX LD SELA SELB 3 x 8Decoder A B OPR ALU SELD

  4. Input R1 R2 R3 R4 R5 R6 R7 MUX MUX LD SELA SELB 3 x 8Decoder A B OPR ALU SELD General Register Organization Examples:

  5. 0 1 2 3 4 5 6 7 8 9 10 Stack Stack Organization • LIFO Last In First Out DR CurrentTop of StackTOS 0 1 2 3 SP 0 0 5 5 FULL EMPTY 0 0 0 8 0 0 2 5 Stack Bottom 0 0 1 5

  6. 0 1 2 3 4 5 6 7 8 9 10 Stack Stack Organization • PUSH SP ← SP – 1 M[SP] ← DR If (SP = 0) then (FULL ← 1) EMPTY ← 0 DR CurrentTop of StackTOS CurrentTop of StackTOS 1 6 9 0 1 6 9 0 0 1 2 3 SP 0 0 5 5 FULL EMPTY 0 0 0 8 0 0 2 5 Stack Bottom 0 0 1 5

  7. 0 1 2 3 4 5 6 7 8 9 10 Stack Stack Organization • POP DR ← M[SP] SP ← SP + 1 If (SP = 11) then (EMPTY ← 1) FULL ← 0 DR CurrentTop of StackTOS CurrentTop of StackTOS 1 6 9 0 1 6 9 0 0 1 2 3 SP 0 0 5 5 FULL EMPTY 0 0 0 8 0 0 2 5 Stack Bottom 0 0 1 5

  8. Stack Organization • Memory Stack • PUSH SP ← SP – 1 M[SP] ← DR • POP DR ← M[SP] SP ← SP + 1 Memory 0 PC 1 Program 2 AR 100 101 Data 102 200 Stack SP 201 202

  9. Reverse Polish Notation • Infix Notation A + B • Prefix or Polish Notation + AB • Postfix or Reverse Polish Notation (RPN) AB + (2) (4)  (3) (3)  + (8) (3) (3)  + (8) (9) + 17 RPN AB + C  D ABC D +

  10. Reverse Polish Notation • Example (A + B)  [C (D+E) + F] (AB +) (DE +) C F + 

  11. Reverse Polish Notation • Stack Operation (3) (4)  (5) (6)  + PUSH 3 PUSH 4 MULT PUSH 5 PUSH 6 MULT ADD 6 4 5 30 3 12 42

  12. CPU Organization • Single Accumulator • Result usually goes to the Accumulator • Accumulator has to be saved to memory quite often • General Register • Registers hold operands thus reduce memory traffic • Register bookkeeping • Stack • Operands and result are always in the stack

  13. Instruction Formats • Three-Address Instructions • ADD R1, R2, R3 R1 ← R2 + R3 • Two-Address Instructions • ADD R1, R2 R1 ← R1 + R2 • One-Address Instructions • ADD M AC ← AC + M[AR] • Zero-Address Instructions • ADD TOS ← TOS + (TOS – 1) • RISC Instructions • Lots of registers. Memory is restricted to Load & Store Instruction Opcode Operand(s) or Address(es)

  14. Instruction Formats Example: Evaluate (A+B)  (C+D) • Three-Address • ADD R1, A, B ; R1 ← M[A] + M[B] • ADD R2, C, D ; R2 ← M[C] + M[D] • MUL X, R1, R2 ; M[X] ← R1  R2

  15. Instruction Formats Example: Evaluate (A+B)  (C+D) • Two-Address • MOV R1, A ; R1 ← M[A] • ADD R1, B ; R1 ← R1 + M[B] • MOV R2, C ; R2 ← M[C] • ADD R2, D ; R2 ← R2 + M[D] • MUL R1, R2 ; R1 ← R1  R2 • MOV X, R1 ; M[X] ← R1

  16. Instruction Formats Example: Evaluate (A+B)  (C+D) • One-Address • LOAD A ; AC ← M[A] • ADD B ; AC ← AC + M[B] • STORE T ; M[T] ← AC • LOAD C ; AC ← M[C] • ADD D ; AC ← AC + M[D] • MUL T ; AC ← AC  M[T] • STORE X ; M[X] ← AC

  17. Instruction Formats Example: Evaluate (A+B)  (C+D) • Zero-Address • PUSH A ; TOS ← A • PUSH B ; TOS ← B • ADD ; TOS ← (A + B) • PUSH C ; TOS ← C • PUSH D ; TOS ← D • ADD ; TOS ← (C + D) • MUL ; TOS ← (C+D)(A+B) • POP X ; M[X] ← TOS

  18. Instruction Formats Example: Evaluate (A+B)  (C+D) • RISC • LOAD R1, A ; R1 ← M[A] • LOAD R2, B ; R2 ← M[B] • LOAD R3, C ; R3 ← M[C] • LOAD R4, D ; R4 ← M[D] • ADD R1, R1, R2 ; R1 ← R1 + R2 • ADD R3, R3, R4 ; R3 ← R3 + R4 • MUL R1, R1, R3 ; R1 ← R1  R3 • STORE X, R1 ; M[X] ← R1

  19. Addressing Modes • Implied • AC is implied in “ADD M[AR]” in “One-Address” instr. • TOS is implied in “ADD” in “Zero-Address” instr. • Immediate • The use of a constant in “MOV R1, 5”, i.e. R1 ← 5 • Register • Indicate which register holds the operand Instruction Opcode Mode ...

  20. Addressing Modes • Register Indirect • Indicate the register that holds the number of the register that holds the operand MOV R1, (R2) • Autoincrement / Autodecrement • Access & update in 1 instr. • Direct Address • Use the given address to access a memory location R1 R2 = 3 R3 = 5

  21. Memory 100 101 102 103 104 Addressing Modes • Indirect Address • Indicate the memory location that holds the address of the memory location that holds the data AR = 101 0 1 0 4 1 1 0 A

  22. Memory 0 1 2 100 101 102 103 104 Addressing Modes • Relative Address • EA = PC + Relative Addr Program PC = 2 + Data AR = 100 1 1 0 A Could be Positive or Negative(2’s Complement)

  23. Memory 100 101 102 103 104 Addressing Modes • Indexed • EA = Index Register + Relative Addr Useful with “Autoincrement” or “Autodecrement” XR = 2 + AR = 100 Could be Positive or Negative(2’s Complement) 1 1 0 A

  24. Memory 100 101 102 103 104 Addressing Modes • Base Register • EA = Base Register + Relative Addr Could be Positive or Negative(2’s Complement) AR = 2 + 0 0 0 5 BR = 100 0 0 1 2 0 0 0 A Usually points to the beginning of an array 0 1 0 7 0 0 5 9

  25. Types of Instructions • Data Transfer Instructions • Data Manipulation Instructions • Program Control Instructions Data value is not modified

  26. Data Transfer Instructions

  27. Data Manipulation Instructions • Arithmetic • Logical & Bit Manipulation • Shift

  28. 1 0 1 1 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 Program Control Instructions Subtract A – B but don’t store the result Mask

  29. ALU Status Bits Cn-1 A B Cn F V Z S C Fn-1 Zero Check

  30. Conditional Branch Instructions

  31. Conditional Branch Instructions • Example: • A: 1 1 1 1 0 0 0 0 • B: 0 0 0 1 0 1 0 0 A: 1 1 1 1 0 0 0 0 +(−B): 1 1 1 0 1 1 0 0 1 1 0 1 1 1 0 0 C = 1 Z=0 S=1 V=0

  32. Program Interrupts • Save: • PC • Registers • Status Bits • Main Program • • • • • • • • • 10 CMA • 11 • • 12 STA [201] • • • • • • • • • • Interrupt • ISR • • • Load AC • • • • • RET Program Status Word PSW

  33. ISR • • • • • • • • • RET Types of Interrupts • External Interrupts • Keyboard, Mouse … etc • Internal Interrupts • Timers, Divide-By-Zero … etc • Software Interrupts • Main Program • • • • • • • • • 10 INT • 11 • • • • •

  34. CISC • Complex Instruction Set Computer • Large number of instructions with a complicated ALU • Some instructions perform specialized tasks and are used infrequently • Large variety of addressing modes • Variable length instruction formats • Instructions can manipulate operands in memory

  35. RISC • Reduced Instruction Set Computer • Relatively few instructions, hence simple ALU • Relatively few addressing modes • Memory access limited to “load” and “store” • All operations done within “registers” of the CPU • Fixed-length and easily decoded instruction format • Single-cycle instruction execution • Hardwired control unit

  36. Homework Chapter 8 • 8-1 • 8-3 • 8-7 • 8-8 • 8-9 • 8-11 • 8-13 • 8-14 • 8-15 • 8-16 • 8-17 • 8-18 • 8-32

  37. Homework • Mano

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