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EE-354. Integrated Circuit Technology. CMOS Fabrication (with extended comments). Oxide Isolation. G. G. D. D. +V DD. -V SS. S. S. p +. p +. p +. n +. n +. n +. p-well. Field oxide. CMOS FABRICATION TECHNOLOGY.

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slide1

EE-354

Integrated Circuit Technology

CMOS Fabrication

(with extended comments)

cmos fabrication technology

Oxide

Isolation

G

G

D

D

+VDD

-VSS

S

S

p+

p+

p+

n+

n+

n+

p-well

Field oxide

CMOS FABRICATION TECHNOLOGY

The following discussion will concentrate on the well-established CMOS fabrication technology, which requires that both n-channel (nMOS) and p-channel (pMOS) transistors be built on the same chip substrate. To accommodate both nMOS and pMOS devices, special regions must be created in which the semiconductor type is opposite to the substrate type. These regions are called wells or tubs. A p-well is created in an n-type substrate or, alternatively, an n- well is created in a p-type substrate. In the simple n-well CMOS fabrication technology, the nMOS transistor is created in the p-type substrate, and the pMOS transistor is created in the n-well, which is built-in into the p-type substrate.

p-MOSFET

n-MOSFET

cmos fabrication technology3

Oxide

Isolation

G

G

D

D

+VDD

-VSS

S

S

p+

p+

p+

n+

n+

n+

p-well

Field oxide

CMOS FABRICATION TECHNOLOGY

The simplified process sequence for the fabrication of CMOS integrated circuits on a p- type silicon substrate is shown.

  • The process starts with the creation of the n-well regions for pMOS transistors, by impurity implantation into the substrate.
  • Then, a thick oxide is grown in the regions surrounding the nMOS and pMOS active regions.
  • The thin gate oxide is subsequently grown on the surface through thermal oxidation.
  • These steps are followed by the creation of n+ and p+ regions (source, drain and channel-stop implants).
  • Finally the metallization is created (creation of metal interconnects).

Metallization

basic processing steps
Basic Processing Steps

Note that each processing step requires that certain areas are defined on chip by appropriate masks. Consequently, the integrated circuit may be viewed as a set of patterned layers of doped silicon, polysilicon, metal and insulating silicon dioxide. In general, a layer must be patterned before the next layer of material is applied on chip. The process used to transfer a pattern to a layer on the chip is called lithography.

The sequence starts with the thermal oxidation of the silicon surface, by which an oxide layer of about 1 micrometer (1000 nm) thickness, for example, is created on the substrate, see (b). The entire oxide surface is covered with a layer of photoresist, which is a light-sensitive, acid-resistant organic polymer, initially insoluble in the developing solution (c). The photoresist material is exposed to ultraviolet (UV) light, the exposed areas become soluble so that the they are no longer resistant to etching solvents. To selectively expose the photoresist, we have to cover some of the areas on the surface with a mask during exposure. Thus, when the structure with the mask on top is exposed to UV light, areas which are covered by the opaque features on the mask are shielded. In the areas where the UV light strikes the photoresist, it is “exposed” and becomes soluble in certain solutes (d).

photoresist
PhotoResist
  • PhotoResist normally comes in powder form, which is insensitive to light. It is reconstituted into liquid form by adding a solvent, typically alcohol.
  • The wafer is mounted on a turntable, spinning slowly, and the photoresist is discharged into its center. Centrifugal force spreads the resist outward across the wafer. The thickness that remains on the wafer is a function of the rate of wafer spin and the viscosity of the photoresist. The thickness is monitored by light diffraction, which is used to adjust the spin rate to reach the correct PR thickness.
  • After the PR is applied, the wafer is heated (~160C) to evaporate the solvent, leaving a smooth solid coating.

Phase Interference gives Photoresist Thickness

photoresist6
PhotoResist
  • The wafer is protected from light, and is put into the photo-lithography tool.Lightis focussed on the wafer, delineating the IC pattern.
  • The wafer is removed and immersed in aDeveloper Solution. If the PR is “positive” resist, then those areas which received light will dissolve away. Negative resist reacts the opposite way, with those areas which were NOT exposed to light being dissolved. This step will leave holes in the resist layer.
  • The wafer is then heated to harden the patterned resist so that it will withstand immersion into acids. A typicalhardening bakeis ~300C.
  • The wafer then re-enters the processing line, for eitheretching or deposition in the patterned holes. In rare cases, the photoresist is not adequate as a mask itself, and the patterns are processed to make a more robust mask, e.g. of thick SiO2 (for very high energy implants) or Si3N4 for solvent etches which also attack PR.

Photo Lithography Exposure Tool

photoresist7
PhotoResist

PhotoResist is used for two functions:

  • Delineation for Etching. A blanket deposition is made on the wafer, then photoresist patterning covers the areas to be SAVED. After developing, the wafer is etched and all parts NOT COVERED by photoresist are removed.
  • Delineation for Deposition. For ion implantation, areas are opened for doping the silicon. The photoresist absorbs all ions except for the areas which are open. In these areas (e.g. Drain or Source wells) the ions penetrate into the silicon.
  • A second Deposition function for photoresist is for patterning thin layers which adhere readily to the wafer. For example, a thin layer of Ti (200A) may be deposited through a PR mask to act as “glue”. The PR openings are so steep, that the Ti film is discontinuous at the edges of the openings. When the PR is removed, it automatically lifts off the blanket Ti deposition, leaving behind Ti only in the PR holes. This process is called deposition processing by “Lift Off”.
basic processing steps8
Basic Processing Steps

The type of photoresist which is initially insoluble and becomes soluble after exposure to UV light is called positive photoresist.

Following the UV exposure step, the unexposed portions of the photoresist can be removed by a solvent. Now, the silicon dioxide regions which are not covered by hardened photoresist can be etched away either by using a chemical solvent (HF acid) or by using a dry etch (plasma etch) process (e). Note that at the end of this step, we obtain an oxide window that reaches down to the silicon surface (f). The remaining (unexposed) photoresist can be stripped from the silicon dioxide surface by using another solvent, leaving the patterned silicon dioxide feature on the surface, see (g).

The fabrication of semiconductor devices requires several such pattern transfers to be performed on silicon dioxide, polysilicon, and metal. The basic patterning process used in all fabrication steps, however, is quite similar to the one shown.examined.

basic processing steps9
Basic Processing Steps

The result of a single lithographic patterning sequence on silicon dioxide, without showing the intermediate steps. Compare the unpatterned structure (top) and the patterned structure (bottom). It took 9 steps to make this simple hole:

  • Oxidize silicon surface
  • Deposit photoresist
  • Anneal photoresist
  • Mount mask above silicon
  • Expose to UV light
  • Develop photoresist
  • Etch photoresist exposed to UV
  • Etch SiO2 through photoresist hole
  • Remove photoresist
making a cmos device 1
Making a CMOS Device - 1
  • The process starts with the oxidation of the silicon substrate (a), in which a relatively thick silicon dioxide layer (5000A), also called field oxide, is created on the surface (b). Then, the field oxide is selectively etched to expose the silicon surface on which the MOS transistor will be created (c). Following this step, the surface is covered with a thin, high-quality oxide layer (25A), which will eventually form the gate oxide of the MOS transistor (d). On top of the thin oxide, a layer of polysilicon (polycrystalline silicon, 3000A) is deposited (e). Polysilicon is used both as gate electrode material for MOS transistors and also as an interconnect medium in silicon integrated circuits. Undoped polysilicon has relatively high resistivity. The resistivity of polysilicon can be reduced, however, by doping it with impurity atoms.
  • After deposition, the polysilicon layer is patterned and etched to form the interconnects and the MOS transistor gates (f). The thin gate oxide not covered by polysilicon is also etched away, which exposes the bare silicon surface on which the source and drain junctions are to be formed (g). The entire silicon surface is then doped with a high concentration of impurities, either through diffusion or ion implantation (in this case with donor atoms to produce n-type doping).
making a cmos device 2
Making a CMOS Device - 2
  • (h) shows that the doping penetrates the exposed areas on the silicon surface, ultimately creating two n-type regions (source and drain junctions) in the p-type substrate. The impurity doping also penetrates the polysilicon on the surface, reducing its resistivity. Note that the polysilicon gate, which is patterned before doping actually defines the precise location of the channel region and, hence, the location of the source and the drain regions. Since this procedure allows very precise positioning of the two regions relative to the gate, it is also called a self-aligned process.
  • Once the source and drain regions are completed, the entire surface is again covered with an insulating layer of silicon dioxide (i). The insulating oxide layer is then patterned in order to provide contact windows for the drain and source junctions (j).
making a cmos device 3
Making a CMOS Device - 3
  • The surface is covered with evaporated aluminum (5000A) which will form the interconnects (k). Finally, the metal layer is patterned and etched, completing the interconnection of the MOS transistors on the surface (l). Usually, a second (and third) layer of metallic interconnect (>5000A) can also be added on top of this structure by creating another insulating oxide layer, cutting contact (via) holes, depositing, and patterning the metal.
cmos n well process
CMOS n-Well Process
  • We have covered (1) the basic process steps for pattern transfer through lithography, and (2) gone through the fabrication procedure of a single n-type MOS transistor. Now we consider the fabrication sequence of n-well CMOS integrated circuits. Shown are both the top view of the lithographic masks and a cross-sectional view of the relevant areas.
  • The n-well CMOS process starts with a moderately doped (impurity concentration ~1016/cm3) p-type silicon substrate. Then, an initial thick “field” oxide layer (5000A) is grown on the entire surface. The first lithographic mask defines the n-well region. Donor atoms, usually phosphorus, are implanted through this window in the oxide. Once the n-well is created, the active areas of the nMOS and pMOS transistors can be defined. The next figures show the significant milestones that occur during the fabrication process of a CMOS inverter.
  • Following the creation of the n-well region, a thick field oxide is grown around the transistor active regions, and a thin gate oxide (25A) is grown on top of the active regions.
cmos n well
CMOS n-Well
  • The polysilicon layer (3000A) is deposited using chemical vapor deposition (CVD) and patterned by dry plasma etching. The created polysilicon lines will function as the gate electrodes of the nMOS and the pMOS transistors and their interconnects. Also, the polysilicon gates act as self-aligned masks for the source and drain implantations that follow this step

Polysilicon Gate Connections

cvd chemical reactions

Continuous gas flow

Diffusion of reactants

Boundary layer

Deposited film

Silicon substrate

CVD Chemical Reactions
  • SiH4(gas) + O2(gas)  SiO2(solid) + 2H2 (gas)
  • SiH4(gas) + H2(gas) +SiH2(gas)  2H2(gas) + PolySilicon (solid)
cmos n well16
CMOS n-Well
  • Using a set of two masks, the n+ and p+ Source and Drain regions are implanted into the substrate and into the n- well, respectively.
  • The ohmic contacts to the substrate and to the n-well are implanted in this process step.

(If a doped silicon region is partially doped to >1018/cm3, then metal contacts to that volume are almost always ohmic (no Shottkey Barrier effect). The possibility of a Shottkey Barrier effect is always possible, and care must be made of the selection of doping and metal contacts.)

Isolation layer

(discussed later)

cmos n well17
CMOS n-Well
  • An insulating silicon dioxide layer is deposited over the entire wafer using CVD (5000A). This is for passivation, the protection of all the active components from contamination.
  • The contacts are defined and etched away to expose the silicon or polysilicon contact windows. These contact windows are necessary to complete the circuit interconnections using the metal layer, which is patterned in the next step.
  • (CVD = Chemical Vapor Deposition, where reactive gases collide above the wafer, and chemical reaction products then fall onto the wafer creating a new layer.)
cmos n well18
CMOS n-Well
  • Metal (aluminum, >5000A) is deposited over the entire chip surface using metal evaporation, and the metal lines are patterned through etching. Since the wafer surface is non-planar, the quality and the integrity of the metal lines created in this step are very critical and are ultimately essential for circuit reliability.
  • Since the metal connects two separate devices, it is called Local Interconnect. The connection of adjacent devices is often called LI-1, as being the lowest level of interconnection.
interconnection materials
Interconnection Materials
  • Polysilicon interconnects are used to connect Gates and other short-distance connections which have minimal currents. Polysilicon is a very stable material that rarely interacts with nearby materials.
  • Metal interconnects have 3-5x the speed of polysilicon (electron mobility is higher) and less resistance. However, metals may react with nearby materials, and may have to be encapsulated using nitrides (e.g. Si3N4 or TiN) to prevent unwanted reactions, or partial erosion in subsequent etching procedures. This is expensive. In Upper Metallurgy (not local interconnects) metal is always used because processing is simple: only Metal + SiO2.
cmos n well20
CMOS n-Well
  • The composite layout and the resulting cross-sectional view of the chip, showing one nMOS and one pMOS transistor (built-in n-well), the polysilicon and metal interconnections.
  • The final step is to deposit a full SiO2passivation layer (5000A), for protection, over the chip, except for wire-bonding pad areas.
  • If the wafer will be stored for some months, a final thin blanket layer of Si3N4 may be applied to prevent penetration by water vapor. Completed FEOL wafers are sometimes stored for more than a year before processing in a BEOL factory.
cmos n well21
CMOS n-Well

The patterning process by the use of a succession of masks and process steps is conceptually summarized below. It is seen that a series of SEVEN masking steps and 34 process steps

must be sequentially performed for the desired patterns to be created on the wafer surface. An example of the end result of this sequence is shown as a cross-section on the right.

advanced cmos technologies
Advanced CMOS Technologies

Twin-Tub (Twin-Well) CMOS Process

  • This technology provides the basis for separate optimization of the nMOS and pMOS transistors, thus making it possible for threshold voltage, body effect and the channel transconductance of both types of transistors to be tuned independently. Generally, the starting material is a n+ or p+ substrate, with a lightly doped epitaxial layer (~1015/cm3) on top. This epitaxial layer provides the actual substrate on which the n-well and the p-well are formed. Since two independent doping steps are performed for the creation of the well regions, the dopant concentrations can be carefully optimized to produce the desired device characteristics.
  • In the conventional n-well CMOS process, the doping of the well region is typically about one order of magnitude higher than the substrate, which, among other effects, results in unbalanced drain parasitics (possible latchup). The twin-tub process, below, avoids this problem.
advanced cmos technologies23
Advanced CMOS Technologies

For inexpensive and low-performance chips, one may use a heavily doped substrate and omit one well. The substrate should be doped to about 1016/cm3, with a resistivity of about 1 Ω-cm. This allows simpler construction, with good “Ground Potential” distribution, but the devices are not optimal and there is a chance of latch-up if the voltages are pushed hard.

For high-performance chips, one uses a low doped substrate, 1015/cm3, 10 Ω-cm, and then constructs Two Wells at optimum doping levels (called Tubs in the diagram). Since the substrate is lightly doped, there is less chance for latch-up because of the high resistivity.

Substrate for Twin-Well MOS Technogy

advanced cmos technologies24
Advanced CMOS Technologies

Silicon-on-Insulator (SOI) CMOS Process

  • Rather than using silicon as the substrate material, an insulating substrate will improve process characteristics such as speed and latch-up susceptibility. The SOI CMOS technology allows the creation of independent, completely isolated nMOS and pMOS transistors virtually side-by-side on an insulating substrate. The main advantages of this technology are the higher integration density (because of the absence of well regions), complete avoidance of the latch-up problem, and lower parasitic capacitances compared to the conventional n-well or twin-tub CMOS processes. A cross-section of nMOS and pMOS devices in created using SOI process is shown below.
references
References
  • CMOS Digital Integrated Circuit Design - Analysis and Design by S.M. Kang and Y. Leblebici
  • W. Maly, Atlas of IC Technologies, Menlo Park, CA: Benjamin/Cummings, 1987.
  • A. S. Grove, Physics and Technology of Semiconductor Devices, New York, NY: John Wiley & Sons, Inc., 1967.
  • G. E. Anner, Planar Processing Primer, New York, NY: Van Nostrand Rheinhold, 1990.
  • T. E. Dillinger, VLSI Engineering, Englewood Cliffs, NJ: Prentice-Hall, Inc., 1988.
  • S.M. Sze, VLSI Technology, New York, NY: McGraw-Hill, 1983.
new concepts in this lecture
New Concepts in this Lecture
  • Single Well Construction – Only need to construct one “well” if use p+ or n+ substrate. (2,3)
  • Photoresist– 5 step process for application and patterning. Can be used for Deposition, Etching or Deliniation (4-7)
  • Self aligned Gate– Make Gate structure so it automatically aligns source/drain. (10,11)
  • Field Oxide– General protection to devices is given by depositing thick SiO2 layer at beginning (13)
  • Interconnects– Basic devices may be connected together with either metal or polysilicon bands, depending on the expected signal current. (19)
  • Twin-Tub CMOS– Uses p or p- substrates to prevent latchup and cross-talk, but requires separate tubs for the pMOS and nMOS devices (22)
  • CMOS on SOI– By putting CMOS circuits on SOI (silicon on insulator) the substrate capacitance is eliminated (2x increase in speed) and cross-talk/latchup is eliminated. (24)