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Understanding RISC Architecture: Metrics, Cycles, and Pipelining in Processor Design

This lecture recap explores the architectural design of processors, focusing on Reduced Instruction Set Computer (RISC) principles. It covers essential topics such as various metrics in processor design, instruction set architecture, assembly instructions, and instruction encoding. The execution cycle of RISC instructions is detailed, highlighting the five main phases: Instruction Fetch, Instruction Decode/Register Fetch, Execution, Memory Operation, and Register Write. Additionally, the concept of pipelining is discussed, illustrating how parallelism can enhance execution efficiency, while addressing potential hazards and challenges in implementation.

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Understanding RISC Architecture: Metrics, Cycles, and Pipelining in Processor Design

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  1. Computer ArchitectureLecture 2 Abhinav Agarwal Veeramani V.

  2. Quick Recap • Various metrics in design of processor • The interface & internal structure • Instruction Set Architecture • Assembly instructions • Instruction encoding add r1, r2, r3

  3. Outline • RISC • Multi-cycle execution • Pipelining

  4. Reduced Instruction Set Computer (RISC) • Limited no. of instructions • Fixed Length • Simple to decode • Easier to implement in hardware • Prevalent in all commercial processors at the core level • Counterpart – C(omplex)ISC • Intel processors • Multi-operation instructions • Still Intel processors have switched to RISC at second level

  5. Execution Cycle of a RISC Instruction Five main phases of Instruction Lifecycle • IF: Instruction Fetch • Read Instruction Memory at PC • Bring the instruction into the CPU • ID/RF: Instruction Decode/Register Fetch • Translate the opcode of the instruction to appropriate control signals • No. of operands • Registers clearly specified in instruction code • Fetch operand values from the registers

  6. Execution Cycle of a RISC Instruction • EX: ALU computation • Activate appropriate functional unit – Adder, Multiplier, Divider, Logical Unit • Why no Subtracter? • MEM: Memory Operation • Load/Store data from/to Data Memory • WR: Register Write • Write the final result value into register

  7. A Picture speaks a thousand words

  8. Multi Cycle Execution • Cycle Per Instruction (CPI) • Kinds of Implementation: • One cycle for each stage • Cycle time determined by longest stage • CPI = ? • Combine all stages into a single cycle • Cycle time determined by worst case instruction • CPI = 1

  9. 000111 00001 00010 00011 Execution Snapshot: Cycle 1 IF PC

  10. 000111 00001 00010 00011 Execution Snapshot: Cycle 2 ID/RF PC Add r1, r2, r3

  11. 000111 00001 00010 00011 Execution Snapshot: Cycle 3 EX PC Add r1, r2, r3 12 2A Adder

  12. 000111 00001 00010 00011 Execution Snapshot: Cycle 4 MEM PC Add r1, r2, r3 12 2A Adder ??

  13. 000111 00001 00010 00011 Execution Snapshot: Cycle 5 WB PC Add r1, r2, r3 Adder

  14. 111001 00001 00100 00000 Execution Snapshot: Cycle 1 IF PC store r1, 0(r4)

  15. Instruction Execution Timeline • Sequential Execution • Low utilization of functional units • Alternative ? store r1, 0(r4) add r1, r2, r3 Instruction Execution Timeline

  16. Pipelining: Concept and Example • Washing machine, Dryer, Iron source: http://cse.stanford.edu/class/sophomore-college/projects-00/risc/pipelining/

  17. Pipelining Concept • Remarkable Insight or Common Sense Time Savings: Per person 0% Overall 42% source: http://cse.stanford.edu/class/sophomore-college/projects-00/risc/pipelining/

  18. Implementation of Pipelining in RISC • Parallelism in all 5 stages • New instruction every cycle • Best case scenario Inst Time

  19. Hardware Requirements source: http://cse.stanford.edu/class/sophomore-college/projects-00/risc/pipelining/

  20. Problems • Data hazards • Dependent Instructions • add r1, r2, r3 • store r1, 0(r4) • Control Hazards • Branches resolution • bnz r1, label • add r1, r2, r3 • label: sub r1, r2, r3 • Structural Hazards

  21. References • Wikipedia: CPU Parallelism http://en.wikipedia.org/wiki/Central_processing_unit#Parallelism • http://www.cs.iastate.edu/~prabhu/Tutorial/PIPELINE/pipe_title.html

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