Download
1 / 6
60 likes | 164 Views
This project from the High-Speed Digital Systems Laboratory at Technion - Israel Institute of Technology focuses on creating a parallel system for high-quality, high-speed image processing, particularly for satellites. By utilizing high-speed controllers and JPEG2000 compressors, the system effectively stores images. The raw data received from the camera is split, compressed in parallel using compressors, and then organized for efficient data packages. The hardware includes Xilinx evaluation boards and FPGA components, while software tools such as ModelSim and Mentor HDL Designer are used for simulation and synthesis.
E N D
Technion - Israel institute of technology department of Electrical Engineering הטכניון - מכון טכנולוגי לישראלהפקולטה להנדסת חשמל High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות דו”ח סיכום פרויקט (סופי( Satellite image compressor controller Performed by: Reshef Dahan & Yifat Manzor Instructor: Eran Segev פרויקט שנתי 1
Abstract המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory This project is aimed to give an answer to the on-going increase of demand for high quality and high speed image processing, especially within the intelligence community. As the years go by, Hi-Tech devices like controllers and processors become more and more fast and efficient. Thus shifting the bottle neck of a data flow to the memory capacity. This situation has created a demand for parallel systems, that can handle a large amount of data in a very short time. This fact is emphasized when the data flow is installed on a satellite and the ability to transmit a large amount of data in short time is essential to the satellite’s mission. In this case the power consumption becomes an important factor as well. In this project we take advantage of a high speed controller capabilities to create a parallel system that is also power-efficient which utilizes JPEG2000 compressors, thus creating a very high speed and high quality image storing system. 2
High speed digital systems laboratory System description המעבדה למערכות ספרתיות מהירות • Raw data is received at high speed of 80MHz rate from the camera • Due to compressors capabilities, power consideration and other system requirements the data is split by the DIVIDER into 3 stripes and sent to 3 compressing units which include the ADV202 JPEG2000 compressors • The data is then compressed in these compression units. Due to the high speed of the divider, the compression is done parallelly in all 3 compression units. • The compressed data is then drawn by the MERGER where it is arranged into neat and well organized data packages. Each package is preceded by it’s own header. This header makes it easy and simple to decompress the data back into an image per demand. 3
High speed digital systems laboratory Specification המעבדה למערכות ספרתיות מהירות • Hardware • Xilinx evaluation board - VirtexIIpro • FPGA component – 2VP30ff1152-6 • JPEG2000 compressors – ADV202 • Software • Aldec Active-HDL • ModelSim ; SimPlus • Mentor HDL Designer • Synthesis – Synplicity Sinplify ; XST • P&R - Xilinx ISE • C environment Simulation – Microsoft Visual Studio. 4
High speed digital systems laboratory System Block Diagram המעבדה למערכות ספרתיות מהירות Xilinx’s development board – Virtex2Pro camera ADV202 FPGA Rocket I\O ADV202 ADV202 Memory 5
High speed digital systems laboratory FPGA Block Diagram המעבדה למערכות ספרתיות מהירות Compression Unit Compresseddata Rocket I/O Compression Unit MERGER DIVIDER (raw data from camera) (to memory) Compression Unit 6
