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Lessons from the field IP/SoC integration techniques that work David Murray, CTO, Duolog. Acknowledgements. Sean Boylan, Duolog Sujatha Sriram, ARM. 4 Pictures – 1 Word. C. O. N. N. E. C. T. Overview. Challenges for IP-based SoC Integration

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lessons from the field ip soc integration techniques that work david murray cto duolog
Lessons from the field

IP/SoC integration techniques that work

David Murray, CTO, Duolog

acknowledgements
Acknowledgements
  • Sean Boylan, Duolog
  • Sujatha Sriram, ARM
overview
Overview
  • Challenges for IP-based SoC Integration
  • Integration methodology (Rules-based)
  • Case-Study/Results
  • Future Directions
ip integration
IP Integration

d

q

d

q

A

B

A1

A2

Out

d

q

Z

d

q

ip based soc integration
IP-Based SoC Integration

IP

  • ARM Based system
    • 4 Processor clusters
    • 3 bus Interconnect systems (CCI/NICx2)
    • 4 sub-systems, (DMC, Peripheral, LCD, Interconnect)
    • 35 independent IP’s to be integrated
    • The AMBA® protocols within the system included APB™, AHB™, AHB-Lite™, AXI™, ATP™, LPI™, AXI4™, APB4™, ACE™ and ACE-Lite™

IP

IP

IP

IP

IP

IP

IP

challenge complexity
Challenge - Complexity

IP

  • Complexity
  • Configurability
  • Standardization
  • Quality
  • Collaboration

IP

IP

IP

IP

IP

IP

IP

ip based soc integration solution
IP-Based SoC Integration Solution
  • IP Interface standardization
  • Efficient SoC Assembly/Connectivity
    • Standard Connectivity
    • Hierarchy Management
    • Configurability
    • Reusability
    • Interoperability
    • Usability!

IP

IP

IP

IP

IP

IP

IP

IP

managing hierarchy
Managing Hierarchy
  • Hierarchy
    • Managing Boundaries
    • Collaboration
    • Fluidity
    • Refactoring
ip interface standardization
IP Interface Standardization

IP

  • Executable IP Interface Specification
    • HW Interface
      • Bus Interfaces
      • Ports (Mapping to bus definition signals)
    • SW Interface
      • Memory Maps
      • Registers
      • Bitfields
  • Consumption
    • IP Automation Flows
    • Integration Flows
  • Industry Standardization
    • IP-XACT
    • Common Bus definitions

Memory Maps

Registers

TX_STATUS

0

Interface

RX_FIFO_CTRL1

4

S

TX_STATUS

8

12

16

RX_FIFO_CTRL1

20

TX_STATUS

24

TX_STATUS

MEMORY_MAP

28

RX_FIFO_CTRL1

32

TX_STATUS

36

40

DMA_SRC_ADD

44

DMA_DST_ADD

48

DMA_CONFIG

52

DMA_CTRL

rules based integration methodology
Select & configure integration-ready IP from libraries

Rules-based system integration

Text-based Integration instructions

Define & refine system hierarchy

Rules-Based Integration Methodology

IP Libraries (Standardized Interfaces)

IP

IP

IP

IP

IP

IP

IP

IP

IP

IP

IP

IP

IP

IP

IP

Integration

Specification

Rules

Synthesis

Fully Integrated Sub-system/Chip

integration instructions
Integration Instructions
  • Powerful Integration Instructions operate on IP Interface metadata

*

CREATE

Component

Periphery

CONNECT

EXPORT

I1

I2

*

Component

Instances

GROUP/

SPLIT

*

I3

I4

IMPORT

*

= Created

*

REFLECT

*

I5

I6

‘0’

INSERT

*

TIEOFF

generic selection mechanism

Informal

Formal

Generic Selection Mechanism
  • Powerful selection mechanism selects the elements

instances.ports

instances(“uart1").ports

instances(“uart1").ports{direction :OUT}

instances(“uart*").ports(“tx")

instances.ports{definition“TX"}

instances.ports{definition“CLK"; bus_definition“CLK_OCP_1_0"}

instances("uart1").ports(“dma*"){definition“INTR_PEND"}

instances(“uart1").ports{definition"port_definition"; direction:OUT}

instances(“uart*").interfaces{definition“APB"; role:SLAVE}

instances{property“DOMAIN", “i_PERIPH_SS"}.ports{definition“RESETDONE"}

instances.ports(exclude(“CLK"))

example
Example

In the sample SubSystem, bring all instance ports of type [Interrupt] up to the next level of hierarchy and prefix the interface ports with the name of the source instance

Integration

Specification

SubSystem

SubSystem

i_ip1

i_ip1

Synthesize

i_ip1_irq_a

irq_a

Irq_a

[Interrupt]

[Interrupt]

[Interrupt]

IP1

IP1

i_ip2

i_ip2

i_ip2_I Inter-b

inter-b

Inter-b

[Interrupt]

[Interrupt]

[Interrupt]

IP2

IP2

i_ip3

i_ip3

i_ip3_N_int_l

N_int_l

N_int_l

[Interrupt]

[Interrupt]

[Interrupt]

IP3

IP3

connection example
Connection Example

ACE Interface has 60+ signals

  • ACADDR
  • ACLK
  • ACLKEN
  • ACPROT
  • ACREADY
  • ACSNOOP
  • ACVALID
  • ARADDR
  • ..

Connect instances(“uP1").interface(“M1"),

instances(“uP1").interface(“S1")

concurrent integration
Concurrent Integration

Main Rules file

External Rules file

Rule : Create Instances

  • Connectivity Ownership
  • Merging or Include
  • Autogenerated IP interfaces

Include external rules files

Rule : PWR/CLK/RESET

Rule : BUS (AMBA)

Rule : Exports

Rule : Interrupts

Rule : DFT

Rule : IP Specific

Rule : IP Specific

Rule : IP Specific

More users can be added to focus on specific types of connectivity

Rule : Tie-Of

Synthesis

Fully Connected

System

full system creation
Full System Creation

Bus

Definitions

  • Features
    • Synthesis of hierarchical system connectivity
    • Netlist generation
    • Rapid Integration timeframes
    • Integrated with other flows
      • IO, Bus fabric, power, verification

Subsystem

Rules

IP

Sub

System

IP

Synthesis

IP

System

Rules

Subsystem

Rules

IP

Sub

System

IP

Synthesis

Synthesis

IP

Subsystem

Rules

IP

IP

Sub

System

IP

Synthesis

case study arm ip based soc integration
Case-Study

ARM IP-Based SoC Integration

arm ip based system
ARM IP- Based System
  • ARM Based system
    • 4 Processor clusters
    • 3 bus Interconnect systems (CCI/NICx2)
    • 4 sub-systems, (DMC, Peripheral, LCD, Interconnect)
  • 12,000+ lines of verilog code describing connectivity
    • 6-7Weeks to develop normally
    • Many connectivity errors
ip interface standardization1
IP Interface Standardization
  • 35 IP leaf components
  • Most IP had IP-XACT descriptions
  • Additional IP packaging
      • The packaging of each IP, with creation of relevant bus interfaces took 1-2 hours per IP.
  • Utilized 109 IP-XACT bus definitions
ip integration1
IP Integration
  • 3 engineers worked within 3 levels of hierarchy
results
Results
  • The integration of 3 sub-systems, 1 major sub-system and a top-level integration was completed within 4 schedule days.
  • This activity could have taken 35+ working days in the past.

An 8x schedule improvement over previous methods

metrics connectivity day
Metrics - % Connectivity/Day

Merge

CLK/RESET

Export

Connectivity

CPU Tieoff

Interrupts

CPU Packaging

Sub Systems

Interconnect

LCD

Interrupt controller

Team working concurrently

Bus

Interconnect

Utilities Library

TUESDAY

WEDNESDAY

THU

(DM) IST

metrics
Metrics
  • The 3 levels of hierarchy were put together using 41 rules, with 372 instructions.
  • These were synthesized and netlisted to 12,045 lines of Verilog code in total
  • Rules
    • Higher level of abstraction
    • High level of reuse
    • Easier to maintain
    • Higher quality

WEAVER

The average ratio of instructions to lines of Verilog code was 31:1

considerations
Considerations
  • Some members of the team were not familiar with the target architecture and needed to understand the connectivity by walking through the legacy Verilog code
  • Some members were not familiar with Weaver and rules-based approach and needed a quick ramp up
  • The rules layout had to be developed throughout this task
  • Some packaging had to be done within the integration activity
  • Rules optimizations were performed within the integration. This included the creation of macros for commonly repeated tasks.
connect amba function
Connect_AMBA function
  • Raising the level of user abstraction for AMBA connectivity
  • ACE can connect to ACELite,AXI4,AXI3
  • Different tieoffs needed
system configurability
System Configurability
  • User sets specific configuration parameters

Any one of thousands of possible configurations can be generated in less than 7 minutes

  • Rules are designed to handle different configurations

WEAVER

  • Weaver creates a specific configuration of the system.
30x schedule improvement
30x Schedule Improvement??
  • Build 1 of 1000s of systems in 7 minutes
  • Interface standardization – Interrupt controller upgrade in 15 minutes
benefits
Benefits
  • Schedule:
    • It is estimated that once the methodology is deployed, it is reasonable to expect a 10x-15x improvement in schedule for new projects and 20x-30x for derivative projects.
  • Quality
    • This netlist was right-first-time as it passed a previous regression test. IP standardization with formal rules eliminates a lot of tedious errors.
  • Productivity
    • Massive improvements in productivity (10x) is expected with this methodology
future considerations
Future Considerations
  • Interface Standardization
  • Chip-in-a-day
  • Verification Enablement
conclusion 4 pictures 1 word
Conclusion - 4 Pictures – 1 Word
  • To Make ..
  • To Interlace ..
  • To construct ..

W

E

A

V

E

thank you
Thank You
  • Please visit us in Booth 1002