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ENE 311

ENE 311. Lecture 7. p-n Junction. A p-n junction plays a major role in electronic devices. It is used in rectification, switching, and etc. It is the simplest semiconductor devices . Also, it is a key building block for other electronic, microwave, or photonic devices.

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ENE 311

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  1. ENE 311 Lecture 7

  2. p-n Junction • A p-n junction plays a major role in electronic devices. • It is used in rectification, switching, and etc. • It is the simplest semiconductor devices. • Also, it is a key building block for other electronic, microwave, or photonic devices.

  3. Basic fabrication steps The basic fabrication steps for p-n junction include • oxidation, • lithography, • diffusion or ion implanation, • and metallization.

  4. Basic fabrication steps • This process is to make a high-quality silicon dioxide (SiO2) as an insulator in various devices or a barrier to diffusion or implanation during fabrication process. • There are two methods to grow SiO2: dry and wet oxidation, using dry oxygen and water vapor, respectively. • Generally, dry oxidation is used to form thin oxides because of its good Si-SiO2 interface characteristics, while wet oxidation is used for forming thicker layers since its higher growth rate. Oxidation

  5. Basic fabrication steps • This process is called photolithography used to delineate the pattern of the p-n junction. Lithography

  6. Basic fabrication steps • (a) The wafer after the development. • (b) The wafer after SiO2 removal. • (c) The final result after a complete lithography process.

  7. Basic fabrication steps Diffusion & Ion Implantation • This is used to put the impurity into the semiconductor. • For diffusion method, the semiconductor surface not protected by the oxide is exposed to a high concentration of impurity. The impurity moves into the crystal by solid-state diffusion. • For the ion-implantation method, the impurity is introduced into the semiconductor by accelerating the impurity ions to a high-energy level and then implanting the ions in the semiconductor.

  8. Basic fabrication steps • This process is used to form ohmic contacts and interconnections. • After this process is done, the p-n junction is ready to use. Metallization

  9. Thermal equilibrium condition • The most important characteristic of p-n junction is rectification. • The forward biased voltage is normally less than 1 V and the current increases rapidly as the biased voltage increases. • As the reverse bias increases, the current is still small until a breakdown voltage is reached, where the current suddenly increases.

  10. Thermal equilibrium condition • Assume that both p- and n-type semiconductors are uniformly doped. • The Fermi level EF is near the valence band edge in the p-type material and near the conduction band edge in the n-type material.

  11. Thermal equilibrium condition • Electrons diffuse from n-side toward p-side and holes diffuse from p-side toward n-side. • As electrons leave the n-side, they leave behind the positive donor ions (ND+) near the junction. • In the same way, some of negative acceptor ions (NA-) are left near the junction as holes move to the n-side.

  12. Thermal equilibrium condition Space-charge region • This forms 2 regions called “neutral” regions and “space-charge” region. • The space-charge region is also called “depletion region” due to the depletion of free carriers. neutral neutral

  13. Thermal equilibrium condition • Carrier diffusion induces an internal electric field in the opposite direction to free charge diffusion. • Therefore, the electron diffusion current flows from left to right, whereas the electron drift current flows from right to left.

  14. Thermal equilibrium condition • At thermal equilibrium, the individual electron and hole current flowing across the junction are identically zero. • In the other words, the drift current cancels out precisely the diffusion current. Therefore, the equilibrium is reached as EFn = EFp.

  15. Thermal equilibrium condition • The space-charge density distribution and the electrostatic potential  are given by Poisson’s equation as (1) • Assume that all donor and acceptor atoms are ionized.

  16. Thermal equilibrium condition • Assume NA = 0 and n >> p for n-type neutral region and ND = 0 and p >> n for p-type neutral region.

  17. Thermal equilibrium condition • The electrostatic potential  in of the n- and p-type with respect to the Fermi level can be found with the help of and as (2) (3)

  18. Thermal equilibrium condition • The total electrostatic potential difference between the p-side and the n-side neutral region is called the “built-in potential” Vbi. It is written as (5)

  19. a) A p-n junction with abrupt doping changes at the metallurgical junction. • (b) Energy band diagram of an abrupt junction at thermal equilibrium. • (c) Space charge distribution. • (d) Rectangular approximation of the space charge distribution.

  20. Thermal equilibrium condition Ex. Calculate the built-in potential for a silicon p-n junction with NA = 1018cm-3 and ND = 1015 cm-3 at 300 K.

  21. Thermal equilibrium condition Ex. Calculate the built-in potential for a silicon p-n junction with NA = 1018cm-3 and ND = 1015 cm-3 at 300 K. Soln

  22. Depletion Region The p-n junction may be classified into two classes depending on its impurity distribution: • the abrupt junction and • the linearly graded junction.

  23. Depletion Region • An abrupt junction can be seen in a p-n junction that is formed by shallow diffusion or low-energy ion implantation. • The impurity distribution in this case can be approximated by an abrupt transition of doping concentration between the n- and the p-type regions.

  24. Depletion Region • In the linearly graded junction, the p-n junction may be formed by deep diffusions or high-energy ion implantations. • The impurity distribution varies linearly across the junction.

  25. Abrupt junction • Consider an abrupt junction as in the figure above, equation (1) can be written as • The charge conservation is expressed by the condition Q = 0 or

  26. Abrupt junction • To solve equation (5), we need to solve it separately for p- and n-type cases. p-side:

  27. Abrupt junction (7)

  28. Abrupt junction n-side: • Similarly, we can have (8)

  29. Abrupt junction • Let consider at x = 0 (9) We may relate this electric field E to the potential over the depletion region as

  30. Abrupt junction • From (6), we have (11) (10)

  31. Abrupt junction • Substitute (11) into (10), this yields (12)

  32. Abrupt junction • Hence, the space-charge layer width or depletion layer width can be written as (13)

  33. Abrupt junction Ex. Si p-n diode of NA = 5 x 1016 cm-3 and ND = 1015 cm-3. Calculate (a) built-in voltage (b) depletion layer width (c) Em

  34. Abrupt junction Soln (a)

  35. Abrupt junction Soln (b)

  36. Abrupt junction Soln (c)

  37. Abrupt junction • If one side has much higher impurity doping concentration than another, i.e. NA >> ND or ND >> NA, then this is called “one-sided junction”. • Consider case of p+-n junction as in the figure (NA >> ND),

  38. Abrupt junction • Similarly, for n+-p junction of ND >> NA • The electric-field distribution could be written as where NB = lightly doped bulk concentration (i.e., NB = ND for p+-n junction)

  39. Abrupt junction • The maximum electric field Em at x = 0 can be found as • Therefore, the electric-field distribution E(x) can be re-written as (16)

  40. Abrupt junction • The potential distribution can be found from integrating (16) as (17)

  41. Abrupt junction Ex. For a silicon one-sided abrupt junction with NA = 1019cm-3 and ND = 1016 cm-3, calculate the depletion layer width and the maximum field at zero bias.

  42. Abrupt junction Soln

  43. Linearly Graded Junction

  44. Linearly Graded Junction • In this case, the Possion equation (1) is expressed by (18) where a is the impurity gradient in cm-4 and W is the depletion-layer width

  45. Linearly Graded Junction • By integrating (18) with the boundary conditions that the electric-field is zero at W/2, E(x) can be found as (19) • The maximum field Em at x = 0 is (20)

  46. Linearly Graded Junction • The built-in potential is given by (21) and (22)

  47. Linearly graded junction in thermal equilibrium. (a) Impurity distribution. (b) Electric-field distribution. (c) Potential distribution with distance. (d) Energy band diagram.

  48. Linearly Graded Junction Ex. For a silicon linearly graded junction with an impurity gradient of 1020 cm-4, the depletion-layer width is 0.5 μm. Calculate the maximum field and built-in voltage.

  49. Linearly Graded Junction Soln Note:Practically, the Vbi is smaller than that calculated from (22) by about 0.05 to 0.1 V.

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