Faster Logic Manipulation for Large Designs

1. Faster Logic Manipulation for Large Designs Alan Mishchenko Robert Brayton UC Berkeley

2. Overview • Logic representations • Disjoint-support decomposition (DSD) • Motivation • Typical applications • Prevalence in benchmarks • DSD package • Conclusions

3. Logic Representations • Truth tables • Sum of products (SOP, CNF) • Factored forms • BDDs • AIGs and TTs • DSDs (since 1854?) (since 1959) (since 1983) (since 1986) (since 2000) (since 2012)

4. XOR AND AND a b c d Disjoint-Support Decomposition • Representation of a Boolean function as a tree of nodes • Nodes are logic functions (AND, XOR, etc) • Leaf nodes do not overlap (have disjoint support) • DSD is full, if functions are only gates (AND, XOR, MUX) • Invertors, if present, are edge attributes • Comments: • Not every function has a full DSD • If a full DSD exists, it is canonical

5. Pros and Cons of Logic Representations ** symmetry, unateness, NPN canonicity, decomposability, etc

6. Boolean network in SIS f f z z y x x y e a c d b e a b c d Motivation for DSD Use Equivalent AIG in ABC AIG is a Boolean network of 2-input AND nodes and invertors (dotted lines)

7. One AIG Node – Many Cuts Combinational AIG • Each AIG cut represents a different logic node • AIG manipulation with cuts is equivalent to working on many Boolean networks simultaneously f 4-input logic function e a c d b Different cuts for the same node

8. Computing Logic Function of a Cut S P E E D • SOP • BDD • TT • TTs are better than BDDs in terms of memory and runtime • However, both TTs and BDDs obscure Boolean properties • DSD • DSDs take less memory/runtime than BDDs/TTs for practical functions of K inputs (8 < K < 16) • DSDs explicitly represent Boolean properties • Symmetry, unateness, NPN canonicity, decomposition, etc • Very important for practical applications!

9. Rewriting node A  Rewriting node B A A  a c b a c a b Subgraph 2 Subgraph 1 B B 6-LUT a c b a c a b a c a b 6-LUT 6-LUT Subgraph 2 Subgraph 1 6 4 6 Logic Operations on Cut Functions • AIG Rewriting • Technology mapping with Boolean matching 16-input structure composed of three 6-LUTs

10. () a <> b [] () c g f e d DSD and 1-Step DSD • DSD • Represented as a tree whose leaves have disjoint support • DSD is full if functions at nodes are only {AND, XOR, MUX}. • Invertors are edge attributes. • A node without DSD is prime. • 1-step DSD • There exists variable x such that both cofactors w.r.t. x are full DSDs F(a,b,c,d,e,f,g) = AND(a, MUX(b,!XOR(c,d,e),!AND(f,g))) ()=and, <>=mux, []=xor, !=not

11. DSD Computation • DSDs and 1-DSDs represent functions of the cuts in the AIG during mapping or rewriting • At each node, find all K-cuts • Each cut defines a function with at most K inputs • Compute cut’s DSD by composing DSDs of the fanin cuts • Compute NPN canonical form and find it in (or add it to) the unique table in DSD manager • Use computed table to reuse the results of intermediate Boolean operations (such as computing AND of two DSDs) • How many cut functions are DSD or 1-DSD?

12. DSD: Prevalence in Benchmarks Table 1A: Percentages of unique functions, NPN classes, and DSDs for different cut sizes (industrial benchmarks). Table 1B: Percentages of unique functions, NPN classes, and DSDs for different cut sizes (public benchmarks).

13. DSD Package • Similar to BDD package • Maintains canonical forms • Performs Boolean operations • Employs computed table • Different from BDD package • Uses different data structure • Used different normalization rules • Limited to small practical functions (6-16 inputs) • The computed table is more reusable

14. Primitives of DSD Manager • One constant 0 node • One primary input node n • Multi-input AND nodes with ordered fanins • Multi-input XOR nodes with ordered fanins • Three-input MUX nodes • Multi-input PRIME nodes (w/o DSD; with 1-step DSD) • Multi-input PRIME nodes (w/o DSD; w/o 1-step DSD)

15. Usefulness of DSDs • Constructed on-the-fly during cut enumeration • No BDDs • No TTs • Start from elementary variables • Derive resulting DSDs by ANDing fanin DSDs • Canonicized • Unique table (only stores NPN classes of Boolean functions) • Cached • Computed table • If available, the result is returned (e.g. LUT structures matching) • If not available, the result is computed and stored

16. Rules for Canonizing a DSD • Collapsing similar functions • AND((a,b), AND(c,AND(d,e))) = AND(a,b,c,d,e) • Propagating complements to inputs or output • AND(!a, !AND(!b, c))  AND(a, !AND(b, c)) • AND(!a, !XOR(b, c))  AND(a, XOR(b, c)) • AND(a, MUX(b,!AND(c,d),!AND(e,f)))  AND(a,!MUX(b,AND(c,d),AND(e,f))) • Using a single variable • AND(MUX(d, e, f), a, XOR(b, c))  AND(n, XOR(n, n), MUX(n, n, n)) • F = (ab)c and G = d(ef) AND(n, XOR(n, n)) - same NPN class • (Arbitrary but fixed) ordering rules, applied in the increasing order • The node fanins are ordered by their support size • If tie, AND precedes XOR precedes MUX precedes PRIME • If tie, a non-complemented fanin precedes a complemented fanin • If tie, fanins’ fanins are ordered and compared in their selected order • If recursive comparison of fanin subtrees fails to produce a unique order, the fanins’ DSDs are isomorphic and their order is immaterial

17. OR () a !a <> <> b b [] () [] () [] () c c c g g g f f f e e e d d d Example of Canonicizing a DSD F(a,b,c,d,e,f,g) = OR( a, !MUX( b, !XOR(c,!e,d), !AND(f,g) ) ) () !a <> b PN = !abfgced ()=and, <>=mux, []=xor, !=not

18. Examples of Full DSDs (ab) denotes AND(a,b) [ab] denotes XOR(a,b) <abc> denotes MUX(a, b, c) = ab + !ac First two columns contain all canonical forms using this basis

19. Comparing run times with truth tables (TTs) with DSDs Application selected because: LUT structure mapping mitigates structural bias of AIG and improves the quality of regular LUT-mapping useful for new generations of programmable devices mapping requires heavy Boolean manipulation implementation in ABC using TTs is prohibitively slow for large designs Preliminary Results (DSDs vs. TTs) Boolean matching on average 30X faster Total runtime of mapping on average 7X faster 6-LUT 6-LUT 6-LUT 6 4 6 Case Study: LUT structure mapping 16-input structure composed of three 6-LUTs

20. References • Canonical form • R. L. Ashenhurst, “The decomposition of switching functions”. Computation Lab, Harvard University, 1959, Vol. 29, pp. 74-116. • Computation from cofactors • V. Bertacco and M. Damiani, "Disjunctive decomposition of logic functions," Proc. ICCAD ‘97, pp. 78-82. • Computation from cofactors (corrections) • Y. Matsunaga, "An exact and efficient algorithm for disjunctive decomposition", Proc. SASIMI '98, pp. 44-50. • Alternative computations • T. Sasao and M. Matsuura, "DECOMPOS: An integrated system for functional decomposition," Proc. IWLS ’98, pp. 471-477. • S.-I. Minato and G. De Micheli, “Finding all simple disjunctive decompositions using irredundant sum-of-products forms”. Proc. ICCAD’98, pp. 111-117. • Boolean operations • S. Plaza and V. Bertacco, "Boolean operations on decomposed functions", Proc. IWLS ’05. • Applications in synthesis and mapping • A. Mishchenko, R. K. Brayton, and S. Chatterjee, "Boolean factoring and decomposition of logic networks", Proc. ICCAD'08, pp. 38-44.

21. Conclusion • DSDs are an interesting representation • Effective only for small, practical functions! • DSDs reveal Boolean properties and facilitate • Rewriting • Technology mapping • Factoring • DSDs lead to larger scope (cut depth) than TTs • Most operations are local but repeated often • Memory usage and runtime are improved due to • Canonicity (unique table in the DSD manager) • Result caching (computed table in the DSD manager)

22. The End