Faster Logic Manipulation for Large Designs. Alan Mishchenko Robert Brayton University of California, Berkeley. Outline. Motivation Simple, local, iterative computation Millions of 6-16 input functions (“small practical functions” = SPFs) Runtime / memory / quality can be improved
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Alan Mishchenko Robert Brayton
University of California, Berkeley
!a = NOT( a )
(ab) = AND( a, b )
[ab] = XOR( a, b )
<abc> = MUX( a , b , c )
When logic transformations, such as circuit restructuring, technology mapping, and post-mapping optimization, are repeatedly applied to large hardware designs, millions of relatively small (6-16 input) Boolean functions have to be efficiently manipulated. This paper focuses on a novel representation of these small functions, in terms of their disjoint-support decomposition (DSD) structures. A new DSD manipulation package is developed, which allows for faster logic manipulation compared to known methods.