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General

General. Lecturer: Philip Leong (phwl) Tutor: Haile YU (hlyu) WWW: http://www.cse.cuhk.edu.hk/~phwl/teaching/ceg3470/index.html All information about the lecture part of the course (and a link to the tutorial website) will be posted here. They will be updated as we go so look out for changes!

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General

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  1. General • Lecturer: Philip Leong (phwl) • Tutor: Haile YU (hlyu) • WWW: • http://www.cse.cuhk.edu.hk/~phwl/teaching/ceg3470/index.html • All information about the lecture part of the course (and a link to the tutorial website) will be posted here. They will be updated as we go so look out for changes! • Tutorial questions will also be posted here. You must hand in solutions every week starting week 3.

  2. Text and References • Text • J.M. Rabaey, “Digital Integrated Circuits”, Prentice 2002 (make sure you get the second edition). • References • Weste and Harris, “CMOS VLSI Design”, Addison Wesley (3rd edition) 2004

  3. Assessment • Grading Scheme • 50% final exam • 20% project • 20% midterm • 10% homework

  4. Assumed knowledge • ERG2020 (Digital Systems) • combinatorial and sequential circuits • noise immunity, power supply decoupling, fanin, fanout • ELE1110 (Circuit theory) • diode, MOS, BJT models • large and small signal analysis • circuit theory

  5. Objectives • Analysis of digital logic gates (CMOS) • TF, noise margin, loading, propagation delay, fanout, power etc • hand calculations, models, SPICE • Introduction to CMOS VLSI design • fabrication • design and layout • tradeoffs (low power, speed, cost etc) • This course • Gives understanding into how digital logic circuits are designed, analysed and modelled • Requires effort on your part

  6. Introduction Computers & VLSI Analysis of Digital Logic Gates Devices (revision) Inverters Combinatorial logic Sequential logic CMOS VLSI Manufacturing Lecture schedule

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