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Innovations in Sensor Thinning Technology for n-in-p Wafers at MPP-HLL

This document presents advancements in sensor thinning technology at the MPI für Physik and MPI Halbleiterlabor (HLL) in Munich. The process includes the successful completion of n-in-p wafers and integration of ATLAS FE-I3 compatible sensors with varying active thicknesses (75μm and 150μm). Key aspects involve the novel MPP demonstrator utilizing SLID and TSV methods, highlighting advantages over traditional bump bonding. Initial tests show low noise and operational efficiency, with ongoing evaluations on the impact of irradiation on module performance.

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Innovations in Sensor Thinning Technology for n-in-p Wafers at MPP-HLL

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  1. SLID interconnection at MPI/EMFT L. Andricek, M. Beimforde, A. Macchiolo, H.G. Moser, R. Nisius, R.H. Richter, P. Weigell MPI für Physik & MPI Halbleiterlabor (HLL), Munich In collaboration with AIDA WP3 EVO Meeting, 12.04.2011

  2. Sensor thinning technology at MPP-HLL • For the n-in-p wafers the process is completed including step #4. The handle wafer has been used as a support during the ASIC interconnection phase. • Production characteristics: • 8 n-in-p 6“ wafers with ATLAS FE-I3 compatible sensors • Different active thicknesses: 75μm and 150μm. • Complete electrical characterization of pixel devices before and after irradiation – Charge Collection Efficiency (CCE) on strips

  3. Novel MPP demonstrator SLID and TSVs towards a new module concept • Use the present ATLAS FE-I3 chip (not designed for vertical integration) to demonstrate the feasibility of both SLID and TSVs.

  4. EMFT SLID Process • Alternative to bump bonding (less process steps “lower cost” (EMFT)). • Small pitch possible (~ 20 mm, depending on pick & place precision). • Stacking possible (next bonding process does not affect previous bond). • Wafer to wafer and chip to wafer possible. • However: no rework possible.

  5. EMFT SLID Process FE-I3 Cu3Sn Cu6Sn5 27 mm Sensor • Alternative to bump bonding (less process steps “lower cost” (EMFT)). • Small pitch possible (~ 20 mm, depending on pick & place precision). • Stacking possible (next bonding process does not affect previous bond). • Wafer to wafer and chip to wafer possible. • However: no rework possible.

  6. Chip to wafer (with handle wafer) FE-I3 chips on the handle wafer (placed with Datacon machine)  suffer from strong misalignment Sensor wafer Misalignment in the central row of Single Chip Modules (SCM) Only 5 modules with an acceptable misalignment and tilt

  7. MPP-HLL first SLID SCM: chip tuning • Sensor thickness 75 mm with SOI technology • Vbias= 50V with Vdepl ~ 40V • FE-I3 chip thinned to 200 mm Threshold tuned to 2800 e- Threshold noise Unconnected channels:

  8. MPP-HLL first SLID module: Charge Collection 90Sr Source Scans • Unconnected channels: 150 / 2880  ~5% • Inefficiencies possibly related to the misalignment of the chips in the handle wafer. Disconnected channels • MPV in agreement with the expectations scaling the charge obtained with a detector 300 mm thick. d= 75 mm

  9. MPP-HLL second SLID module • All channels are connected and functioning • Noise value comparable to n-in-p SCMs connected by bump-bonding (~170-190 e-) Threshold noise: 183 e- 90Sr Source Scans All channels connected d= 75 mm

  10. TSV in the FE-I3 chips TSV Etching (Bosch process) applied to FE-I3 8” wafers. 60 µm deep TSVs with lateral dimensions of 3 x 10 µm2on the original wire-bonding pads • First etching trials on dummy wafer • Performed in the un-thinned FE-I3 chips of one designated test-wafer • Etched to a depth of ~ 69 mm • Rough cut/break along the long direction of the test structure shows the structure of the vias and of the trench around them • Process plan of the hot FE-I3 wafer • Local planarisation of the fan-out pads by depositing and etching of SACVD-Oxide • Perform via etching and filling in the hot FE-I3 wafer • Connect the readout chip with SLID to the hot sensor wafers

  11. Summary and Outlook • First 2 modules interconnected with SLID were measured: • Chip and sensor working fine with low noise • Interconnection inefficiencies at the corners probably due to misalignment of the chips on the handle wafer • Test of the remaining 3 modules with SLID interconnection is ongoing • Plan to irradiate some of the modules (1-5 x1015 neq cm-2) • Test the SLID+TSV modules when ready (hopefully still this year).

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