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Progress Last Week

Programming of FPGA in LiCAS ADC for Continuous Data Readout Week 4 Report Tuesday 22 nd July 2008 Jack Hickish. Progress Last Week. Behavioural simulation of both continuous and burst modes of operation - Simulations indicated error free - Simulations could not test complete data path

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Progress Last Week

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  1. Programming of FPGAin LiCAS ADC forContinuous Data ReadoutWeek 4 ReportTuesday 22nd July 2008Jack Hickish

  2. Progress Last Week Behavioural simulation of both continuous and burst modes of operation - Simulations indicated error free - Simulations could not test complete data path Implementation of new code onto FPGA chip - Unexplained data output - not matching sinusoidal input - noise at frequencies below 1MHz

  3. Since then… Explanation of data output Signal generator output connected to ADC input via ‘homemade’ adaptor. Unfortunately this adaptor served to short each of the input channel pins. No surprise results didn't make sense! Having found an adaptor to properly connect the ADC to the signal generator, the design was tested with USB DAQ software and Chipscope.

  4. Testing Burst Mode counta (0) and counta(1) show least significant bits of sample counter. When the counter stops counting, the information is written to the USB (via FIFO) in a burst

  5. Testing Burst Mode DAQ software is set so that it acquires twice as many pieces of data as are acquired by the ADC. Hence output is generated sinusoid extending over half of readings

  6. Testing Continuous Mode counta(30) and counta(31) are most significant bits of sample counter. When counter reaches zero it resets (to 0xFFFFFFFF) and data continues to be acquired. Data is being fed into FIFO but note no data in FIFO data out signal.

  7. Testing Continuous Mode As expected from Chipscope signals, no data was being output over USB. - This suggested a problem with the FIFO read enable signal

  8. Testing Continuous Mode When read enable signal was probed, it was found to be low, preventing the FIFO from writing data to the USB. The read enable signal is controlled only by the full flag of the USB controller and the empty flag of the FIFO. i.e. read enabled when FIFO not empty and USB not full Chipscope shows FIFO is not empty, conclusion is that the USB is full even before data begins being acquired.

  9. Testing Continuous Mode Triggering Chipscope before the FPGA begins data acquisition, we see that as soon as Continuous (FFI) mode is selected, the FIFO begins to full.

  10. Testing Continuous Mode Problem can be traced to write enable signal. This signal is the same signal used to control the external FIFO in the case of Burst operation. - The external FIFO has an active low write enable signal - The internal FIFO has an active high write enable As soon as Continuous operation mode is selected, the external write enable signal is diverted to the internal FIFO and causes it to fill. All this happens before the USB software begins acquiring data, hence the USB buffer is full before data acquisition begins. To fix this problem, a well place “not” in the write enable code...

  11. Testing Continuous Mode Data written into FIFO and read out to USB continuously

  12. Testing Continuous Mode Continuous sinusoid, with sample counter resetting at 125 readings. Using USB DAQ set to continuous mode, realtime changes of the input signal can be observed in the onscreen graph.

  13. Testing Continuous Mode • - Qualitative success of continuous system. • - Vigorous test is comparing (bitwise) input signal and output signal for consistency • - Much simpler test is to use inbuilt test mode feature to generate countdown, and compare output data with expected values • - DAQ software editted to output data in numerical as well as graphical form. On comparison with expected output few (but some) errors are seen

  14. Testing Continuous Mode • Possible causes: • - Fundamental timing problems in continuous acquisition code. • - Data acquisition rate too high – greater averaging period required for successful operation.

  15. Other Developments • Currently developing a serial rather than parallel interface between PC and FPGA. • This allows greater flexibility (the planned system (SPI) will require only 4 wires for communication, the current system requires 16). • The SPI (Serial Peripheral Interface) allows 2-way communication, allowing read back of diagnostic information from the ADC (e.g. memory full flags indicating data overflow)‏

  16. The Week Ahead... • Implementation of SPI bus • Further investigation into output data reliability • After that... • Increasing sample registers to allow long period (~1 second) averaging

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