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Correlation Between State and Control Signals in Out-of-Order Issue Logic

Correlation Between State and Control Signals in Out-of-Order Issue Logic. Ken Barr, Ken Conley and Serhii Zhak Checkpoint I: October 19, 2000. Modifications to Project Goals. More data mining, less implementation Abstracted from particular hardware architecture Correlation statistics

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Correlation Between State and Control Signals in Out-of-Order Issue Logic

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  1. Ken Barr, Ken Conley, and Serhii Zhak Correlation Between State and Control Signals in Out-of-Order Issue Logic Ken Barr, Ken Conley and Serhii ZhakCheckpoint I: October 19, 2000

  2. Ken Barr, Ken Conley, and Serhii Zhak Modifications to Project Goals • More data mining, less implementation • Abstracted from particular hardware architecture • Correlation statistics • What control signals occur at moment instruction is fetched? • How consistent is instruction’s path through pipeline? • Register renaming statistics • Quantitative measure of how quickly register resources freed • Use as metric in correlation statistics

  3. Ken Barr, Ken Conley, and Serhii Zhak Preliminary Results • Correlation statistic does not include register renaming, yet • Initial statistics show 50-70% rate of consistency for instruction path • Run with SpecInt95 benchmark suite • Measurement based on mathematical mode • Bimodal distribution giving lower-than-expected results

  4. Ken Barr, Ken Conley, and Serhii Zhak Register Renaming Issues • Register renaming or large register file necessary for OOO performance • Should/does register renaming need to be included in prediction? • Prediction for register renaming depends on consistent renaming • Perfectly consistent renaming equivalent to no renaming (ignoring ISA benefits) • SimpleScalar register renaming not as versatile as we had hoped

  5. Ken Barr, Ken Conley, and Serhii Zhak Examining Renaming • Simplescalar RUU scheme ties renaming to all aspects of OOO execution. • Hard to isolate renamer • We extend Simplescalar to manage a “free list” of physical registers • Also, add per-instruction renaming statistics • Min/max/avg length of “renamedness” • Number of “remaps” • Re-execution counter • Following slides: 500K instructions of a Perl benchmark with 16 RUU_Stations.

  6. Ken Barr, Ken Conley, and Serhii Zhak Reservation Length • Every instruction needs physical register for 3 cycles. • 80% relinquish their mapping within 7 cycles. • This gives hope that a scheme could quickly reassign a mapping • We need to compare this with average CPI

  7. Ken Barr, Ken Conley, and Serhii Zhak Remap Rate • remap rate = samename / repetitions • Discouraging chart! • But there’s some good news: • “Samename” counts only mappings that match the first mapping.Perhaps two-bit-counter or confidence mechanism could enhance this.

  8. Ken Barr, Ken Conley, and Serhii Zhak Progress to Checkpoint 2 and Beyond! • Final version of data mining engines • Investigate bimodal distributions • Build custom test patterns • Run more, longer simulations • Continue work on SimpleScalar for collection of statistics

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