1 / 23

230 likes | 337 Views

Motivation for the Design of an Instruction Set. Consider the invented assembly language instruction add x, y, z y is added to z , and the result is written to x. 4 fields are implied within the machine code for this instruction

Download Presentation
## Motivation for the Design of an Instruction Set

**An Image/Link below is provided (as is) to download presentation**
Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author.
Content is provided to you AS IS for your information and personal use only.
Download presentation by click this link.
While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server.
During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

**Motivation for the Design of an Instruction Set**Consider the invented assembly language instruction add x, y, z y is added to z, and the result is written to x**4 fields are implied within the machine code for this**instruction The number of unique instructions determines the size of the op code field 8 bits will be enough. (MIPS has 6.) z y x addop code addresses (assume 32 bits)**The goal:**Compute how much time it takes to fetch and execute an instruction. Then, by design, make it faster. P M Fact: memory accesses take much longer than processor operations.**processor operation : memory access**1 : 20 ish For this exercise, use 1 : 10 Each memory access transfers 32 bits of data in parallel (or, at one time). This implies that there are 32 wires connecting P to M.**add x, y, z** fetch instruction PC update decode get operands do operation (add) store result requires a memory access**Machine code for this add is more than 96 bits**• instruction fetch requires3 memory accesses • 2 operands to load (y and z) requires2 memory accesses • 1 result to store (x) requires1 memory access**using 1:10 ratio,**62 60/62 is spent waiting for memory !**new approach:**redesign instructions with 2 operands add x, y does x x + y y x addop code addresses (again, 32 bits)**original instruction: add x, y, z**becomes copy x, z add x, y move add + 41 52 = 93**MIPSSPARCALPHAPowerPC**instruction set with • 3 operands is a 3-address architecture • 2 operands is a 2-address architecture • 1 operand is a 1-address architecture Intel x86**1 operand ?**How to add ? from memory Acc to memory add x does Acc Acc + x**add x, y, z**becomes load z # Acc z add y # Acc Acc + y store x # mem Acc an address (again, 32 bits) op code**store**load add + + 21 22 21 = 64**But, what if the example includes more than 1 instruction?**x (y + z) / 3 On the 3 address architecture: add x, y, z div x, x, 3 3 x x immediate div addresses**on the 3-address architecture**add div immediatevalue 3"loaded" atfetch ! + 62 52 = 114**on the 2-address architecture:**copy x, z add x, y div x, 3 must load x, but 3 is in the instruction div copy add + + 41 52 42 = 135**immediatevalue 3 is in the instruction**on the 1-address architecture: load z add y div 3 store x div store load add + + + 21 22 12 21 = 76**The best parts of the ideas:**• Make instructions small, to minimize fetch time • Keep the Accumulator, to avoid extra loads and stores • In fact, we'd like to have several Accumulators. . . all inside the processor call them registers**All modern processors have sets of registers, kept in a**register file. • The MIPS R2000 has a set of 3232-bit registers. . .**These architectures are categorized asload/store**architectures. • operands for arithmetic and logical instructions only come from and go to registers . . . not memory • other instructions (loads and stores) read from or write to memory**Our invented example:**add x, y, z becomes more like load reg1, y load reg2, z add reg3, reg2, reg1 store reg3, x addresses**consider the add instruction**add reg3, reg2, reg1 For 32 registers, it only takes 5 bits. instruction size ≈ 8 + 5+ 5 + 5 = 23 bits**add**load 14 22

More Related