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Design FSM, Instruction Set Architecture

CS147 Lecture 10. Design FSM, Instruction Set Architecture. Prof. Sin-Min Lee. State Machines. Solution: Formulate State Diagram:. Construct a sequence detector: 001. 0. 1. 0. 0. 1. A. B. C. D. 1. 0. 1. 2) Construct State Table:. Present State. Next State.

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Design FSM, Instruction Set Architecture

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  1. CS147 Lecture 10 Design FSM,Instruction Set Architecture Prof. Sin-Min Lee

  2. State Machines • Solution: • Formulate State Diagram: • Construct a sequence detector: 001 0 1 0 0 1 A B C D 1 0 1

  3. 2) Construct State Table: Present State Next State Input (x) Output (PS) Z 0 1 A B A 0 B C A 0 C B D 0 D B A 1

  4. 3) Construct Logic Table Present State Next State Input (x) X=0 X=1 Output (PS) Z Q1 Q0 Q1 Q0 Q1 Q0 A 0 0 0 1 0 0 0 B 0 1 1 1 0 0 0 1 1 0 C 1 1 0 0 0 1 0 0 1 0 1 D

  5. 4) Extract Logic Equations Present State Next State Input (x) X=0 X=1 Output (PS) Z Q1 Q0 Q1 Q0 Q1 Q0 A 0 0 0 1 0 0 0 B 0 1 1 1 0 0 0 1 1 0 C 1 1 0 0 0 1 0 0 1 0 1 D + Q 0= X, Q1= XQ1Q 0 + XQ1Q0, + Z = Q1Q0

  6. 5) Draw Logic Diagram X* D Q0 Q0* + Q0= X clk + X Q1= XQ1Q 0 + XQ1Q0 D Q1 Q1 Q1 And Q0 Or X And Q1 Q0

  7. Continue… Continue… Z = Q1Q0 Q1 And Z Q0 6)Draw functional block diagram 001 Detect Input Output Clock

  8. State Machines • Solution: • Formulate State Diagram: • Construct a soda machine which 1) take only quarters, and • 2) deliver a soda when all three quarters are inserted 25C Not 25C 25C 25C 25C A B C D Not 25C Not 25C 25C

  9. 2) Construct State Table: Present State Next State Input (x) Output (PS) Z 0 1 A A B 0 B A C 0 C A D 0 D A B 1

  10. 3) Construct Logic Table Present State Next State Input (x) X=0 X=1 Output (PS) Z Q1 Q0 Q1 Q0 Q1 Q0 A 0 0 0 0 0 1 0 B 0 1 0 0 1 1 0 1 1 0 C 0 1 0 0 0 0 0 1 1 0 1 D

  11. 4) Extract Logic Equations Present State Next State Input (x) X=0 X=1 Output (PS) Z Q1 Q0 Q1 Q0 Q1 Q0 A 0 0 0 0 0 1 0 1 B 0 1 0 0 1 1 1 0 1 1 0 0 C 0 1 0 0 0 0 0 1 1 1 0 1 D + Q 0= XQ1 + XQ0 Q1= XQ 0, + Z = Q1Q0

  12. 5) Draw Logic Diagram X And D Q0 Q0* + Q0 Q 1= XQ0 clk + X Q0= XQ1 + XQ0 D Q0 Q0 Q1 And Or X And Q0

  13. Continue… Continue… Z = Q1Q0 Q1 And Z Q0 6)Draw functional block diagram Quarters Detect Money Soda Clock

  14. Moore Machine Vs. Mealy Machine Moore machine associates its output with the states. The outputs are represented either within the vertex corresponding to a state or adjacent to the vertex. Mealy machine associates its output with the transitions. Each arc of the input values shows the output values generated during the transition.

  15. What is “Computer Architecture” • Computer Architecture is the design of the computer at the hardware/software interface. • Computer Architecture = Instruction Set Architecture + Machine Organization Computer Architecture Instruction Set Design Machine Organization Computer Interface Hardware Components Compiler/System View Logic Designer’s View

  16. The Instruction Set: a Critical Interface software instruction set hardware

  17. ISA • The instruction set architecture, or ISA, is much like the car interface, but for microprocessors. • ISA includes the information needed to interact with the microprocessor, but not the details of how microprocessor itself is designed and implemented. • ISA is the set of all instructions that the microprocessor can execute.

  18. Language Categories • High-level languages • Platform-independent: the same code can be run on computers with different microprocessors and OSs. • C++, Java, Fortran • Assembly languages • Specific to a microprocessor • Directly manipulate the data stored in internal components • Machine languages • Instructions are binary • Programs are converted to machine language • Each processor has its own machine language

  19. Compiling and Assembling • High-level language programs are compiled. • Assembly language programs are assembled

  20. Compiling • A program written in high-level language, a source code, is input to a compiler. • The compiler checks for syntax errors and generates an object code file, machine language equivalent of the source code. • A linker combines all object codes and stores it as an executable file. • Some programs use the object code of other programs. • A loader copies the executable file into memory

  21. Compilation Process

  22. Assembling • Each assembly language instruction corresponds to one unique machine code instruction. • Assembler are much less complex than compilers

  23. High-level and Assembly • Most software is written in high-level language. • There are many support tools for high-level languages. • Assembly language is used in conjunction with high-level languages to optimize code. • The program is no longer platform-independent

  24. Compilation for Java Applets

  25. Assembly Language Instructions Instruction types: • Data transfer instructions • Data operation instructions • Program control instructions

  26. Instruction Set Architecture • Instruction set architecture is the attributes of a computing system as seen by the assembly language programmer or compiler. This includes • Instruction Set (what operations can be performed?) • Instruction Format (how are instructions specified?) • Data storage (where is data located?) • Addressing Modes (how is data accessed?) • Exceptional Conditions (what happens if something goes wrong?) • A good understanding of computer architecture is important for compiler writers, operating system designers, and general computer programmers.

  27. What is ISA? Aspects of the computer visible to the programmer: • Data Types • Registers • Instructions • Addressing

  28. Instruction Set Architecture as an ADT • “…the attributes of a [computing] system as seen by the programmer, i.e. the conceptual structure (state) and functional behavior (operations), as distinct from the organization of the data flow and controls, the logical design, and the physical implementation.” - Amdahl, Blaauw, and Brooks, 1964 instruction instruction ….. instruction Registers + Memory instruction instruction instruction instruction ….. instruction

  29. 63 63 ·· ·· (j 15) (j 15) 24 24 r3 r3 (beq r0, r1, 2) (beq r0, r1, 2) 8 8 23 23 r2 r2 12 12 (sw r3, 0(r0)) (sw r3, 0(r0)) 22 22 r1 r1 1 20 (lw r2, 1(r0)) (lw r2, 1(r0)) 21 21 r0 r0 2 2 (add r1, r2, r3) (add r1, r2, r3) 20 20 PC PC 21 20 ·· ·· 3 3 7 7 2 2 2 2 1 1 0 0 0 0 4 4 Instruction Set Architecture as an ADT Assumptions  8 bit ISA  # of registers = 4 + PC (Program Counter)  Memory size = 64B Memory Memory Registers Registers add r1, r2, r3 Before Register and Memory After Register and Memory

  30. 63 63 ·· ·· (j 15) (j 15) 24 24 r3 r3 (beq r0, r1, 2) (beqr0, r1, 2) 8 8 23 23 r2 r2 7 12 (sw r3, 0(r0)) (sw r3, 0(r0)) 22 22 r1 r1 20 20 (lw r2, 1(r0)) (lw r2, 1(r0)) 21 21 r0 r0 2 2 (add r1, r2, r3) (add r1, r2, r3) 20 20 PC PC 22 21 ·· ·· 3 3 7 7 2 2 2 2 1 1 0 0 0 0 4 4 Instruction Set Architecture as an ADT Assumptions  8 bit ISA  # of registers = 4 + PC (Program Counter)  Memory size = 64B Memory Memory Registers Registers lw r2, 1(r0) Before Register and Memory After Register and Memory

  31. 63 63 ·· ·· (j 15) (j 15) 24 24 r3 r3 (beq r0, r1, 2) (beq r0, r1, 2) 8 8 23 23 r2 r2 7 7 (sw r3, 0(r0)) (sw r3, 0(r0)) 22 22 r1 r1 20 20 (lw r2, 1(r0)) (lw r2, 1(r0)) 21 21 r0 r0 2 2 (add r1, r2, r3) (add r1, r2, r3) 20 20 PC PC 23 22 ·· ·· 3 3 7 7 2 2 8 2 1 1 0 0 0 0 4 4 Instruction Set Architecture as an ADT Assumptions  8 bit ISA  # of registers = 4 + PC (Program Counter)  Memory size = 64B Memory Memory Registers Registers sw r3, 0(r0) Before Register and Memory After Register and Memory

  32. 63 63 ·· ·· (j 15) (j 15) 24 24 r3 r3 (beq r0, r1, 2) (beq r0, r1, 2) 8 8 23 23 r2 r2 7 7 (sw r3, 0(r0)) (sw r3, 0(r0)) 22 22 r1 r1 20 20 (lw r2, 1(r0)) (lw r2, 1(r0)) 21 21 r0 r0 2 2 (add r1, r2, r3) (add r1, r2, r3) 20 20 PC PC 24 23 ·· ·· 3 3 7 7 2 2 8 8 1 1 0 0 0 0 4 4 Instruction Set Architecture as an ADT Assumptions  8 bit ISA  # of registers = 4 + PC (Program Counter)  Memory size = 64B Memory Memory Registers Registers beq r0, r1, 2 Before Register and Memory After Register and Memory

  33. 63 63 ·· ·· (j 15) (j 15) 24 24 r3 r3 (beq r0, r1, 2) (beq r0, r1, 2) 8 8 23 23 r2 r2 7 7 (sw r3, 0(r0)) (sw r3, 0(r0)) 22 22 r1 r1 20 20 (lw r2, 1(r0)) (lw r2, 1(r0)) 21 21 r0 r0 0 0 (add r1, r2, r3) (add r1, r2, r3) 20 20 PC PC 15 24 ·· ·· 3 3 7 7 2 2 8 8 1 1 0 0 0 0 4 4 Instruction Set Architecture as an ADT Assumptions  8 bit ISA  # of registers = 4 + PC (Program Counter)  Memory size = 64B Memory Memory Registers Registers j 15 Before Register and Memory After Register and Memory

  34. Data Types • Unsigned Integers • Signed Integers • Characters • Floating-point Numbers

  35. Unsigned Integers • Stores the integer in standard binary format 00101011 = 1 + 2 + 8 + 32 = 43

  36. Signed Integers • Stores the integer in two’s complement format to denote sign Steps to convert signed integer to base 10: • Store leading bit, 1 = negative, 0 = positive • Invert all bits • Add 1

  37. Characters • Represented by integer values Many different character encodings exist: • ASCII • UNICODE • UTF-8 • UTF-16

  38. Floating-point Numbers Four components in a floating-point number: • Sign • Mantissa • Radix • Exponent

  39. Registers Registers provide a variety of services: • Instruction Counter • Register-to-Register Operations • Memory-to-Register Operations • Memory-to-Memory Operations • Processor Status

  40. Instruction Counter Register • All von Neumann machines have an instruction counter which is a register

  41. Register-to-Register Registers • Operate on one register using another register (ADD) • Supported by all ISA’s

  42. Memory-to-Register Registers • Operate on memory using a register (LOAD, STORE) • Not supported by all ISA’s

  43. Memory-to-Memory Registers • Operate on one memory location using another memory location (STRCMP) • Not supported by all ISA’s

  44. Processor Status Registers • A collection of registers that indicate the current state of the processor (Carry, Interrupt, Zero) • Different ISA’s use different status registers

  45. Instructions Categories of instructions: • Operate • Memory Access • Control • Miscellaneous

  46. Operate Instructions Typical operations include: • Arithmetic (ADD, SUB, MUL, DIV) • Logical (AND, OR, NOT, XOR) • Shift (ROL, ROR) • Character (STRCMP) • Stack (PUSH, POP)

  47. Memory Access Instructions Typical operations include: • Load (LODSB) • Store (STOSB)

  48. Control Instructions • Conditional Branch (JZ, JC, JO, JS) • Unconditional Branch (JMP)

  49. Miscellaneous Instructions • Input/Output (IN, OUT) • Interrupts (CLI, INT, IRET) • Halt • Privileged

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