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Lecture 9.1

Lecture 9.1. Building a FET. Integrated Circuits. CPU or Memory First Layer Transistors Capacitors Diode Resistors Multi-layer Wiring Interconnects Bonding Pads Dielectric Capacitors Heterostructures. MOSFET in Memory Chip. Source Gate Drain. Field Effect Transistor (FET).

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Lecture 9.1

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  1. Lecture 9.1 Building a FET

  2. Integrated Circuits • CPU or Memory • First Layer • Transistors • Capacitors • Diode • Resistors • Multi-layer • Wiring • Interconnects • Bonding Pads • Dielectric • Capacitors • Heterostructures

  3. MOSFET in Memory Chip Source Gate Drain

  4. Field Effect Transistor (FET)

  5. Voltage Controlled Resistor

  6. Make Mask for Doping • Clean wafer surface • Oxidize Si Surface • How Thick is needed for Doping Mask? • Spin on photoresist • Image photoresist • Develop photoresist • Dissolve un-crosslinked photoresist • Etch exposed SiO2 down to the Si of the wafer • Doping • Remove Implantation Mask

  7. Silicon Oxidation • Reactor • Furnace at T=850C • Pure Oxygen • Si + O2 SiO2 • Kinetics • BL-Mass Transfer • J=Kg(CA-0) • SS-Diffusion • J=DO-SiO2 (dC/dx) • Heat Transfer • BL, q=h(T1-T) • Solid, q=kSiO2(dT/dx) • J=q/Hrxn Grxn<0, Spontaneous

  8. Kinetics • Thickness • Linear Rate • Reaction Control • First Order • BL-MT Control • BL-HT Control • Parabolic Rate • Product diffusion Control • Product heat transfer Control • J =(dx/dt) SiO2/MW SiO2

  9. Thickness Experiments • Parabolic Rate • Derive it! • dx2/dt=2K • K=Ko exp(-Ea/RgT) • x=o @ t=0 • x=  at t=  • Very common!! • Slow Solid State Diffusion • Slow Heat Conduction

  10. Mask Thickness • To effectively prevent ions penetrating in thick zone • Relatively thick Oxide Protection layer • Patterned • Thinning (etching) of Oxide Protection layer over implantation zone • Remove oxide layer with impurities inside

  11. Mask Thickness • Transmission through mask • T=1/2 erfc[(x-xave)/2 x] • To stop 99.99% of implanted materials, T=10-4 • Solve for x, the thickness to stop 99.99% of ions.

  12. SiO2 Mask Thickness

  13. Si3N4 Mask Thickness

  14. Photoresist Mask Thickness

  15. Implantation • Create Ions in Vacuum • Accelerate in Electric Field • Impinge onto Silicon Surface • Knock out Si ion(s) • Charge Balance • Travel deep into Silicon

  16. Implantation • Effect of Ion Mass

  17. Implant Depth Depth Increases with Energy

  18. Implantation Straggle Increases with Energy

  19. Implantation Concentration Profile • Probability Based • N(x)=Nmax exp[(x-xave)2/2x2] • Nmax=(Ndose/[(2) x])~(0.4 Ndose/ x) • Ndose=Qdose/e • Qdose= current applied/cm2 • σx = projected straggle

  20. Remove Implantation Mask • Chemical Mechanical Polishing • Remove all Oxide from wafer surface • Dry Etching

  21. Drive Dopant Impurities into Wafer • Heat Treating • Laser Annealing • Diffusion • Heat and Hold for period of time • Solid State Diffusion • dC/dt=D d2C/dx2 • C=Co at x=0 • C=0 at x=

  22. Concentration Profile time

  23. Diffusion of Implanted Dopants • Diffusion Furnace or Laser • Heat Treatment • Solid State Diffusion • dCA/dt = CT d/dz(DAB dXA /dz) • C=Co(z) = CT XA(z) at z=0 • C=0 at z= • DAB =(D*A XB + D*B XA) (d ln [aA]/d ln [XA]) • Interdiffusion or mutual diffusion coefficient

  24. Gate Oxide • Capacitor connecting Gate to center of npn or pnp heterojunction • Capacitance • Area • Thickness • Dielectric constant of oxide

  25. Field Effect Transistor (FET)

  26. Gate Oxide Capacitance C=oA/d =C/Co =1+e e = electric susceptibility

  27. Field Effect Transistor (FET)

  28. Thickness Experiments • Parabolic Rate • Derive it! • dx2/dt=2K • K=Ko exp(-Ea/RgT) • x=o @ t=0 • x=  at t=  • Very common!! • Slow Solid State Diffusion • Slow Heat Conduction

  29. Metalization • Transistor Contacts • Base • Emitter • Gate • Planarize/Polish layer to get Flat Surface for next lithography Step • Metal Deposition

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