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Lecture 4: ISA Introduction

Lecture 4: ISA Introduction. Architecture vs. Implementation Basic machine organization Machine state Opcodes/Operands Register organization Instruction Semantics. Review of Computer Architecture:. Dally slide goes here. Instruction Set Architecture.

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Lecture 4: ISA Introduction

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  1. Lecture 4: ISA Introduction Architecture vs. Implementation Basic machine organization Machine state Opcodes/Operands Register organization Instruction Semantics

  2. Review of Computer Architecture: Dally slide goes here

  3. Instruction Set Architecture • Contract between programmer and the hardware • Defines visible state of the system • Defines how state changes in response to instructions • Programmer: ISA is model of how a program will execute • Hardware Designer: ISA is formal definition of the correct way to execute a program • ISA specification • The binary encodings of the instruction set

  4. data program ALU pc control Stored Program Computer Model • The “von-Neumann” memo • Storage • Program • Data • Program counter • ALU

  5. Mem Mem Regs Regs Before State After State ISA Basics instruction Instruction formats Instruction types Addressing modes Op Mode Ra Rb Data types Operations Interrupts/Events Machine state Memory organization Register organization

  6. Architecture vs. Implementation • Architecture: defines what a computer system does in response to a program and a set of data • Programmer visible elements of computer system • Implementation: defines how a computer does it • Sequence of steps to complete operations • Time to execute each operation • Hidden “bookkeeping” functions

  7. Why Separate ISA from Implementation? • Compatibility • VAX architecture: mainframe  single chip • ARM: 20x performance range • high vs. low performance, power, price • Longevity • 20-25 years of ISA • x86 in 7th generation of implementations (architecture families) • enhancements at generation boundaries • retain software investment • amortize development costs over multiple markets

  8. Examples • Architecture or Implementation? • Number of GP registers • Width of memory bus • Binary representation of the instruction sub r4,r2,#27 • Number of cycles to execute FP instruction • How condition code bits are set on a move instruction • Size of the instruction cache • Type of FP format

  9. PC Memory Byte Addr R0-R31 Little Endian 32 bit 32-bit addr Machine State Machine State • Registers • Size/Type • Program Counter (= IP) • accumulators • index registers • general registers • control registers • Memory • Visible hierarchy (if any) • Addressibility • byte, word, bit • byte order (endian-ness) • maximum size • protection/relocation

  10. opcode src1 src2 dst Components of Instructions • Operations (opcodes) • Number of operands • Operand specifiers • Instruction encodings • Instruction classes • ALU ops (add, sub, shift) • Branch (beq, bne, etc.) • Memory (ld/st) add r1,r2,r3 src1

  11. Operand Number • No Operands HALT NOP • 1 operand NOT R4 R4  R4 JMP _L1 • 2 operands ADD R1, R2 R1  R1 + R2 LDI R3, #1234 • 3 operands ADD R1, R2, R3 R1  R2 + R3 • > 3 operands MADD R4,R1,R2,R3 R4 R1+(R2*R3)

  12. Effect of Operand Number Assign E = (C+D)*(C-D) C  r1 D  r2 E  r3 3 operand machine 2 operand machine mov r3,r1 add r3,r2 sub r2,r1 mult r3,r2 add r3,r1,r2 sub r4,r1,r2 mult r3,r4,r3

  13. Operand Types How do we specify an operand? 1) We don’t - operands can be implicit Example: x86 RET (return address implicitly at top of stack) 2) We include operand specifiers a) Name (usually explicit) b) Namespace (usually implicit)

  14. Examples: NOT R4 ADD r1,r5,4000 register name Register name Memory Address Name Spaces • Each name space  separately enumerable set of names • For typical machine • Register numbers • Memory addresses • Name space implied by opcode:

  15. Describing Operands Name Space OP • 2 choices • Universal operand specifiers • include space and name • Name space specific • space implied by operation • name in operand field Implicit RET INC Register 5 DEC Memory 0x5000 OP Name RET 5 INCR DECM 0x5000

  16. In the beginning…the accumulator 2 instruction types: op and store A  A op M A  A op *M *M  A a one address architecture each instruction encodes one memory address 2 addressing modes immediate: M direct addressing: *M Early machines: EDVAC, EDSAC... Evolution of Register Organization FFF Memory PC Accumulator 0 Machine State Address (M) Op Instruction Format (Op encodes addressing mode)

  17. Why Accumulator Architectures? • Registers expensive in early technologies (vacuum tubes) • Simple instruction decode • Logic also expensive • Critical programs were small (efficient encoding) • Less logic  faster cycle time • Model similar to earlier “tabulating” machines • Think adding machine

  18. Add an indexed addressing modeA  A op (M+I) *(M+I)  A good for array access: x[j] address of x[0] in instruction j in index register one register for each key function IP  instructions I  data addresses A  data values new instructions to use I INC I, CMP I, etc. The Index Register FFF Index Memory PC Accumulator 0 Machine State Address (M) Op Instruction Format

  19. Example of Indexed Addressing sum = 0; for(i=0; i<n; i++) sum = sum + y[i]; START: CLR i CLR sumLOOP: LOAD IX AND #MASK OR i STORE IX LOAD sumIX: ADD y STORE sum LOAD i ADD #1 STORE i CMP n BNE LOOP START: CLRA CLRXLOOP: ADDA y(X) INCX CMPX n BNE LOOP With Index Register Without Index Register

  20. But What About... sum = 0; for(i=0; i<n; i++) for(j=0; j<n; j++) sum = sum + x[j]*y[i];

  21. Merge accumulators (data) and index (address) Any register can hold variable or pointer simpler more orthogonal (opcode independent of register usage) More fast local storage but….addresses and data must be same size How many registers? More - fewer loads and stores But - more instruction bits General Registers FFF PC Rn-1 Memory R1 R0 0 Machine State i j k Op 3-address Instruction Format

  22. Register state is PC and SP All instructions performed on TOS (top of stack) and SOS pushes/pops of stack implied op TOS SOS op TOS M op TOS *M op TOS *(M+SP) Many instructions are zero address Stack cache for performance similar to register file hardware managed Why do we care? JVM Memory PC Cur Inst SP Code TOS TOS SOS Stack Stack $ Stack Machines

  23. Examples of Stack Code a = b + c * d; e = a + f[j] + c; PUSH d PUSH c MUL PUSH b ADD PUSH j PUSHX f PUSH c ADD ADD POP e LOAD R1, d LOAD R2, c MUL R3, R1, R2 LOAD R4, b ADD R5, R4, R3 LOAD R6, j LOAD R7, f(R6) ADD R8, R7, R2 ADD R9, R5, R8 STORE e, R9 PUSH d MUL c ADD b PUSH j PUSHX f ADD c ADD POP e Pure Stack One Address Stack Load/Store (zero addresses) (many GP registers) 8 inst, 7addr 10 inst, 6addr 11 inst, 7 addr

  24. Summary • ISA definition • system state (general/special registers, memory) • the effect of each operation on the system state • Next Time • Addressing modes • Data types • Common instruction types • Case study: DLX

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