Fault-Tolerant design of RF front-end circuits

1. Fault-Tolerant design of RF front-end circuits P.R. Mukund, Ph.D. Gleason Professor of Electrical Engineering Director, RF/Analog/Mixed-signal Lab (RAMLAB) Rochester Institute of Technology Rochester, NY 14623

2. Funding Acknowledgements – Acknowledgements –

3. Motivation SoC, SiP implementations High levels of integration Complex interaction between RF, analog, & digital domains Heightened sensitivity to package parasitics, wide tolerances

4. Need for Fault-tolerance in RF circuits

5. Background Self-test solutions with high overheads Computation, real-estate, DSP, power ATE testing very expensive (40% of chip cost)

6. Summary of Prior Work

7. Prior BIST Architecture

8. Feedback for RF circuits?

9. This work…. Alternative fault-tolerance methods for RF circuits Overcome limitations of traditional feedback Emphasis on low overhead, minimally intrusive, low-cost solutions Robust circuitry/algorithms for error-free operation Low-frequency/DC post-processing No DSP/off-chip processing, ultra-fast

10. Methodology: ‘Locked loop’ concept Remove constraints of feedback RF forward – sample resistor, amplify a little, gain variation does not matter Baseband – dc : BiSTRemove constraints of feedback RF forward – sample resistor, amplify a little, gain variation does not matter Baseband – dc : BiST

11. ‘Locked Loop’ approach To sense a signal which is indicative of the performance metric of the circuit

12. Minimally Intrusive Sensing HF transient current has all info, including input match Bypass ground return capacitors – aviod high impedance of bond wire, bumps, etc Output side faults – mixer HF transient current has all info, including input match Bypass ground return capacitors – aviod high impedance of bond wire, bumps, etc Output side faults – mixer

13. Non-intrusive sensing Eliminate resistor for circuits with source-degenerative coils No measurable intrusion on LNA performance Over a narrow-frequency range, the source-coil can provide similar current-information as the resistor Gain and S22 sensed from source coil of mixer: accounts for matching network

14. Quantifying Specifications Gain sensed directly at mixer, using a third tone. Peak-peak value of this signal is a direct measure of gain

15. Variable S11: The tapped coil Ls too small to change freq of S11 CGS changes both freq and magnitudeLs too small to change freq of S11 CGS changes both freq and magnitude

16. Variable Gain and S22 S22: Bank of varactors at output node Gain: Variable Transconductance array

17. Self-correction algorithm Linear search, not maximally efficient: but simpler circuitry and ease of implementation. Linear search, not maximally efficient: but simpler circuitry and ease of implementation.

18. Sensor chain Source follower for isolation More stages for higher gain PD output stored on capacitors Op-amps for buffers, comparators Basic digital logic

19. Results - Sensor chain

20. Simulation results - LNA

21. Experimental Results (1)

22. Experimental Results (2) Tapped Coil performance S11 magnitude stayed below -20 dB for all taps Match frequencies were: 1.737 GHz, 1.925 GHz, 2.03 GHz and 2.125 GHz.

23. S22 and Gain correction (I)

24. S22 and Gain Correction (II)

25. Overheads Same circuitry re-used for all specifications Area overhead less than 10% of cascode LNA Can be re-used for other circuits of Front-end Losses in switches of the gate-coil NF degradation by 0.2 - 0.3 dB Power overheads Additional circuitry switched on only for duration of self-calibration – negligible power overhead Current-splitting transconductance array uses additional current (5% - 10% overhead)

26. Summary Fault-tolerant RF design has great relevance and applicability in an RFIC world of increasing complexity and massive integration Alternate, novel methodology for fault-tolerance in GHz domain Minimal overheads, no topological revision Ultra-fast (200 us) compared to existing test schemes (order of 100s of ms) Robust algorithms and post-processing techniques Demonstrated in silicon

27. Publications (1) Journal Papers Tejasvi Das, Anand Gopalan, Clyde Washburn and P.R. Mukund, “Self-calibration of RF front end circuitry”, IEEE Transactions on Circuits and Systems, Dec 2005 Tejasvi Das, Anand Gopalan, Clyde Washburn and P.R. Mukund, “Towards Fault-tolerant RF front-ends”, Journal of Electronic Testing (JETTA), Accepted for publication (Issue release Sep.06) Anand Gopalan, M. Margala and P.R. Mukund, “A current based self-test methodology for RF front-end circuits”, Microelectronics Journal, No.36, Aug 2005 Anand Gopalan, Tejasvi Das, Clyde Washburn and P.R. Mukund, “BiST for Multi-GHz CMOS RF Front-ends”, IEEE Transactions on Circuits and Systems (Under review) Conference Papers “Self-calibration of Gain and Output match in LNAs”, IEEE ISCAS May 2006, Kos, Greece “Towards Fault-Tolerant RF Front-Ends: On-Chip Input Match Self-Correction of LNAs”, The IEEE Mixed-signal Test Workshop, June 2005, Cannes, France. “Dynamic Input match correction in RF Low Noise Amplifiers”, 19th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, Oct. 2004, Cannes, France

28. Publications (2) Conference papers (contd.) “Use of Source Degeneration for Non-Intrusive BIST of RF Front-end Circuits”, Proceedings of the International Symposium on Circuits and Systems, Kobe, Japan, May 2005 An Ultra-fast, on-chip BiST for RF LNAs”, 18th IEEE International Conference on VLSI Design, India, Jan. 2005.

29. References (1) [1] B. Razavi, “RF CMOS transceivers for cellular telephony”, IEEE Communications Magazine, Vol. 41, No. 8, pp.144 – 149, August 2003. [2] B. A. Floyd, C.-M. Hung, K. K. O, “Intra-Chip Wireless Interconnect for Clock Distribution Implemented With Integrated Antennas, Receivers, and Transmitters”, IEEE Journal of Solid-State Circuits, vol. 37, no. 5, pp. 543-552, May 2002. [3] M.-C. F. Chang, V. P. Poychowdhury, L. Zhang, H. Shin, Y. Qian, “RF/Wireless Interconnect for Inter- and Intra-Chip Cpmmunications”, Proceedings of the IEEE, vol. 89, no. 4, pp.456-466, April 2001. [4] J.M.V Santos Dos, J.M.M Ferreira, “Fault-tolerance: new trends for digital circuits”IEEE International Conference on Electronics, Circuits and Systems, Vol 3,  pp. 237 – 240, Sept. 1998 [5] Michael S. Heutmaker, Duy K. Le, “Architecture for self-test of a wireless communication system using sampled IQ modulation and boundary scan”, IEEE Communications Magazine, Vol. 37, No. 6, pp. 98-102, June 1999. [6] Madhuri Jarwala, Duy Le, Michael S Heutmaker, “End-to-end test strategy for wireless systems” Proceedings of the IEEE International Test Conference (TC), pp. 940-946, 1995. [7] N. Nagi, A. Chatterjee, H. Yoon, J. A. Abraham, “Signature analysis for analog and mixed-signal circuit test response compaction”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 17, No. 6, pp. 540-546, June 1998. [8] Rajsuman R., “Iddq testing for CMOS VLSI”, Proceedings of the IEEE, Vol.88 No. 4, pp. 544 –568, April 2000.

30. References (2) [9] Isern E., Figueras J., “Test generation with high coverages for quiescent current testing of bridging faults in combinational systems”, Proceedings of the International Test Conference, pp. 73 -82, October 1993. [10] A. Gopalan, T. Das, C. Washburn and P.R. Mukund, “An ultra-fast on-chip BiST for RF CMOS LNAs”, Proceedings of 18th International conference on VLSI Deign, January 2005, pp.485 – 490 [11] J.M.V Santos Dos, J.M.M Ferreira, “Fault-tolerance: new trends for digital circuits” IEEE International Conference on Electronics, Circuits and Systems, Vol 3, Sept.1998 pp. 237 - 240 [12] M. Soma, “Challenges and approaches in mixed signal RF testing” Proceedings of the Tenth Annual IEEE International ASIC Conference, Sept. 1997, pp. 33 – 37 [13] E. Liu, W. Kao, E. Felt, A. Sangiovanni-VIncentelli, “Analog testability analysis and fault diagnosis using behavioral modeling”, Proceedings of the IEEE Custom Integrated Circuits Conference, May 1994, pp. 413 – 416 [14] Yu.V Malyshenko, “Functional fault models for analog circuits”, IEEE Design & Test of Computers, Volume 15,  Issue 2,  April-June 1998, pp. 80 – 85 [15] Anand Gopalan, P.R.Mukund and Martin Margala, “A Non-Intrusive Self-Test Methodology for RF CMOS Low Noise Amplifiers”, IEEE Mixed-signal Test workshop, Portland, June 2004. [16] Thomas H. Lee, “The Design of CMOS Radio-Frequency Integrated Circuits”, Cambridge University Press, 1998. [17] John Ferrario, Randy Wolf, Steve Moss, Mustapha Slamani, “A low-cost test solution for wireless phone RFICs”, IEEE Communications Magazine, v 41, n 9, September, 2003, pp. 82-89

31. Thank You