332 578 deep submicron vlsi design lecture 8 design margin l.
Download
Skip this Video
Loading SlideShow in 5 Seconds..
332:578 Deep Submicron VLSI Design Lecture 8 Design Margin PowerPoint Presentation
Download Presentation
332:578 Deep Submicron VLSI Design Lecture 8 Design Margin

Loading in 2 Seconds...

play fullscreen
1 / 22

332:578 Deep Submicron VLSI Design Lecture 8 Design Margin - PowerPoint PPT Presentation


  • 507 Views
  • Uploaded on

332:578 Deep Submicron VLSI Design Lecture 8 Design Margin. David Harris and Mike Bushnell Harvey Mudd College and Rutgers University Spring 2005. Outline. Supply Voltage Temperature Process Variation Design Corners Matching Delay Tracking Summary. Material from: CMOS VLSI Design

loader
I am the owner, or an agent authorized to act on behalf of the owner, of the copyrighted work described.
capcha
Download Presentation

PowerPoint Slideshow about '332:578 Deep Submicron VLSI Design Lecture 8 Design Margin' - pebbles


An Image/Link below is provided (as is) to download presentation

Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author.While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server.


- - - - - - - - - - - - - - - - - - - - - - - - - - E N D - - - - - - - - - - - - - - - - - - - - - - - - - -
Presentation Transcript
332 578 deep submicron vlsi design lecture 8 design margin

332:578 Deep SubmicronVLSI DesignLecture 8 Design Margin

David Harris and Mike Bushnell

Harvey Mudd College and Rutgers University

Spring 2005

outline
Outline
  • Supply Voltage
  • Temperature
  • Process Variation
  • Design Corners
  • Matching
  • Delay Tracking
  • Summary

Material from: CMOS VLSI Design

By Neil E. Weste and David Harris

Deep Submicron VLSI Des. Lec. 8

distributions
Distributions
  • Model design variations as uniform (normal) Gaussian distributions

Deep Submicron VLSI Des. Lec. 8

uniform distribution
Uniform Distribution
  • Specified with half-range
  • Accept variations all over the entire half-range
  • Example: Specify VDD at 1.2V +/- 10%

Deep Submicron VLSI Des. Lec. 8

normal distribution
Normal Distribution
  • Specify with standard deviation s
  • Retain parts with 3s distribution –
    • Means 0.26% of parts rejected
  • Retain parts with 2s distribution –
    • Means 4.56% of parts rejected
  • Retain parts with 1s distribution –
    • Means 31.74% of parts rejected
  • 2s or 3s is common
  • Designers moving to statistical, not worst-case, design

Deep Submicron VLSI Des. Lec. 8

temperature
Temperature
  • As T rises, ID decreases
  • Transistor junction T = Ambient T + T due to package power dissipation
    • Determined by PTOTALand package Thermal R
  • Verify commercial parts for 110 ºC ≤ TJUNCTION≤ 125 ºC

Deep Submicron VLSI Des. Lec. 8

process variation
Process Variation
  • In film thickness, lateral dimensions, dopings
  • Measured:
    • From wafer to wafer
    • From die to die – inter-die
    • Across die – intra-die or process tilt

Deep Submicron VLSI Des. Lec. 8

important device variations
Important Device Variations
  • Channel length L
    • Photolithography proximity effects
    • Optics deviations
    • Plasma etch dependencies
  • Oxide thickness tox
    • Well-controlled -- only significant between wafers
  • Threshold voltageVt
    • Varying dopings
    • Annealing effects
    • Mobile Q in gate oxide
    • Discrete dopant variations (few dopant atoms in transistors)

Deep Submicron VLSI Des. Lec. 8

interconnect variations
Interconnect Variations
  • Line width and line spacing
    • Photolithography
    • Etching proximity effects
  • Metal and dielectric thickness
    • Chemical Mechanical Polishing
  • Contact resistance
    • Contact dimensions
    • Etch and clean steps

Deep Submicron VLSI Des. Lec. 8

design corners
Design Corners
  • Design or Process Corners = Processing + Environmental Variations
  • Box surrounding guaranteed circuit performance

Deep Submicron VLSI Des. Lec. 8

process corners
Process Corners
  • F = Fast, T = Typical, S = Slow
  • Corner specified with 5 letters for:
    • nMOS, pMOS, Wire, VDD, T
  • Corner specified with 4 letters for:
    • nMOS, pMOS, VDD, T
  • Corner specified with 3 letters for:
    • nMOS, pMOS, environment
  • Corner specified with 2 letters for:
    • nMOS, pMOS
  • Circuits most apt to fail at Design Space Corners
    • Must be simulated at all corners to guarantee operation

Deep Submicron VLSI Des. Lec. 8

design corner checks
Design Corner Checks

Deep Submicron VLSI Des. Lec. 8

environmental corners
Environmental Corners

Deep Submicron VLSI Des. Lec. 8

matching
Matching
  • Must frequently have pairs of transistors with closely-matched electrical parameters
    • Sense amplifier – offset V depends on matching
    • Analog circuit differential pairs
    • Clock tree – clock skew depends on mismatch
  • Mismatch due to:
    • Systematic variability
      • Example – ion implanter gives different dose to different chip parts
      • Can be modeled and nulled out
    • Uncertainty
      • Source unknown, random, or too costly to model

Deep Submicron VLSI Des. Lec. 8

controlling variability
Controlling Variability
  • Vt variations scale with:
  • Device parameters depend on:
    • Size
    • Orientation
    • Nearby polysilicon density
  • Build identical, large transistors oriented in same direction
  • Surround transistor with consistent poly pattern
  • Vt variations due mainly to statistical fluctuations in # dopant atoms

Deep Submicron VLSI Des. Lec. 8

matching problems
Matching Problems
  • Systematic
    • Factors that can be modeled & simulated at design time (wires of different lengths)
  • Random
    • Most process variations in L, Vt, or interconnect
  • Drift
    • T – change slowly with time, compared to f
    • Null out by compensation circuits
  • Jitter
    • Happens at f comparable to system clock – cannot be eliminated through feedback

Deep Submicron VLSI Des. Lec. 8

delay tracking
Delay Tracking
  • Best way is to replicate gates being matched
  • Example:
    • Use replica bit lines in static RAM to decide when sense amp. Should fire
      • Any mismatch in wire, gate, diff. C happens in both wires
    • Use chain of AND plane devices in PLA to determine when to activate OR plane
  • Not practical in many situations
    • Use a chain of inverters, instead, for matching
    • Needs a nominal delay 30% greater than that of matched path

Deep Submicron VLSI Des. Lec. 8

fo4 delays vs process
FO4 Delays vs. Process

Deep Submicron VLSI Des. Lec. 8

fo4 delays vs supply v
FO4 Delays vs. Supply V

Deep Submicron VLSI Des. Lec. 8

fo4 delays vs t
FO4 Delays vs. T

Deep Submicron VLSI Des. Lec. 8

fo4 delays vs worst case design corner
FO4 Delays vs. Worst-Case Design Corner

Deep Submicron VLSI Des. Lec. 8

summary
Summary
  • Fringing Field Capacitance
  • Crosstalk
    • Crosstalk Delay
    • Crosstalk Noise
  • Inductance – Important for bond wires to package and signal integrity
    • Now important for internal chip interconnect

Deep Submicron VLSI Des. Lec. 8