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ECE 448 FPGA and ASIC Design with VHDL. Spring 2007. ECE 448 Team. Course Instructor : Kris Gaj kgaj@gmu.edu. Lab Instructors (TAs) :. Tuesday & Wednesday section s : Nghi Nguyen former MS CpE student nguyen.nghi@gmail.com Thursday section: Hoang Le

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slide2

ECE 448 Team

Course Instructor:Kris Gaj

kgaj@gmu.edu

Lab Instructors (TAs):

Tuesday & Wednesday sections:

Nghi Nguyen

former MS CpE student

nguyen.nghi@gmail.com

Thursdaysection:

Hoang Le

MS CpE student, specializing in Digital Systems Designhle7@gmu.edu

slide3

ECE 448 Team – Division of Tasks

Course Instructor – Primary Responsibilities

  • Lectures
  • Preparing and grading exams and quizzes
  • - Coordination of work on development
  • of new experiments
  • Instructions for the lab experiments
  • Coordination of work done by the TAs
  • Enforcing consistent policies and grading standards
  • Mid-semester student satisfaction survey
  • Resolving conflicts and providing feedback to the TAs
  • Holding office hours
slide4

ECE 448 Team – Division of Tasks

Lab Instructors (TAs) – Primary Responsibilities

  • Teaching hands-on sessions on how to use software, hardware and testing equipment needed for experiments
  • Introductions to the lab experiments
  • Grading student demonstrations and reports
  • Holding office hours
  • Development and testing of new lab experiments
slide5

Course hours

  • Lecture:
  • Tuesday, Thursday
  • 5:55-7:10 PM, Robinson Hall A, room 111
  • Lab Sessions:
  • Tuesday, Wednesday, Thursday 7:20-10:00 PM, S&T 2, room 203
  • Office hours:
    • Monday, TBD, room 203, Nghi Nguyen
    • Monday, 6:00-7:00 PM, room 223, Kris Gaj
    • Tuesday, TBD, room 203, Nghi Nguyen
    • Tuesday, 7:30-8:30 PM, room 223, Kris Gaj
    • Wednesday, TBD, room 203, Hoang Le
    • Thursday, 7:30-8:30 PM, room 223, Kris Gaj
slide6

ECE 448 Section Assignment Rules

  • You are welcome to attend any of the
  • multiple office hour sessions
  • Please attend the class meetings of the other section only
  • in case of emergency and give preference in access
  • to the lab computers to the students attending
  • the right section
  • All experiment demonstrations need to be done
  • in the presence of your TA, and can be
  • done exclusively during the class time of your section
slide7

Lab Access Rules and Behavior Code

Please refer to the FPGA Design & Test Lab website:

http://ece.gmu.edu/labs/fpgalab.htm

slide8

Grading criteria

First part of the semester (before the Spring break)

Lab experiments & homework - Part I

(individual assignments)

20%

Quizzes: 5%

Midterm exam for the lecture: 10%

Midterm exam for the lab: 15%

Second part of the semester (after the Spring break)

Lab experiments & homework - Part II   

(group assignments)

20%

Quizzes: 5%

Final exam

25%

slide9

Spring 2007 Enrollment as of January 23, 2007

Undeclared

1

BS in EE

11

BS in CpE

20

slide10

Digital Systems & Computers

Color code:

Old Curriculum

BS EE

ECE 280

PHYS 261

PHYS 265

BS CpE

 C

or

ECE 331

ECE 332

 C

 C

ECE 445

 C

 C

ECE 367

ECE 442

ECE 448

ECE 447

ECE 492

ECE 493

slide11

Digital Systems & Computers

Color code:

New Curriculum

BS EE

ECE 280

PHYS 261

PHYS 265

BS CpE

or

 C

ECE 331

ECE 332

 C

 C

ECE 448

ECE 445

 C

ECE 492

CS 222

CS 367

ECE 447

ECE 493

slide12

Transition from ECE 449 to ECE 448

starting in Spring 2006

ECE 449

NEW COURSE, ECE 448

4 credit

hours

1 credit

hour

VHDL intro

+ FPGA intro

+ ASIC intro

+ more advanced

lectures on

applications and

platforms

Lab

Lecture

VHDL intro

+ FPGA intro

+ hands-on tools intro

+ experiment intro

+ lab time

Lab

hands-on tools intro

+ experiment intro

+ lab time

slide13

ECE 448, FPGA and ASIC Design with VHDL

Topics

VHDL:

- writing synthesizable RTL level code in VHDL

- writing test benches

FPGAs:

- architecture of FPGA devices

- tools for the computer-aided design with FPGAs

- current FPGA families & future trends

slide14

High-level ASIC Design:

- standard cell implementation approach

- logic synthesis tools

- differences between FPGA & standard-cell ASIC design flow

Applications:

- basics of computer arithmetic

- applications from communications, cryptography,

digital signal processing, bioengineering, etc.

Platforms:

  • FPGA boards
  • microprocessor board–FPGA board interfaces: PCI, PCI-X
  • reconfigurable computers

New trends:

  • using high-level programming languages to design hardware
  • microprocessors embedded in FPGAs
slide15

Tasks of the course

Comprehensive

introduction to

FPGA & front-end ASIC

technology

Advanced

course on digital

system design

with VHDL

Testing

equipment

  • hardware:
    • Xilinx FPGAs,
    • TSMC library
    • of standard ASIC
    • cells
  • software:
    • VHDL simulators
    • Synthesis tools
    • Xilinx ISE
  • writing VHDL code
  • for synthesis
  • design using
  • finite state machines
  • and algorithmic state
  • machines
  • test benches

- oscilloscopes

- logic analyzer

slide16

VHDL for Specification

VHDL for Simulation

VHDL for Synthesis

levels of design description
Levels of design description

Algorithmic level

Level of description

most suitable for synthesis

Register Transfer Level

Logic (gate) level

Circuit (transistor) level

Physical (layout) level

vhdl design styles

dataflow

VHDL Design Styles

VHDL Design

Styles

  • Testbenches

structural

behavioral

Components and

interconnects

Concurrent

statements

Sequential statements

  • Registers
  • State machines

Subset most suitable for synthesis

testbenches
Testbench Environment

TB Processes

Generating

Stimuli

Design Under Test (DUT)

Testbenches

Stimuli All DUT Inputs

Simulated Outputs

world of integrated circuits
World of Integrated Circuits

Integrated Circuits

Full-Custom

ASICs

Semi-Custom

ASICs

User

Programmable

PLD

FPGA

PAL

PLA

PML

LUT

(Look-Up Table)

MUX

Gates

slide22

Block RAMs

Block RAMs

What is an FPGA?

Configurable

Logic

Blocks

I/O

Blocks

Block

RAMs

slide23

Two competing implementation

approaches

FPGA

FieldProgrammable

GateArray

ASIC

ApplicationSpecific

IntegratedCircuit

  • designed all the way
  • from behavioral description
  • to physical layout
  • no physical layout design;
  • design ends with
  • a bitstream used
  • to configure a device
  • designs must be sent
  • for expensive and time
  • consuming fabrication
  • in semiconductor foundry
  • bought off the shelf
  • and reconfigured by
  • designers themselves
slide24

FPGAs vs. ASICs

FPGAs

ASICs

Off-the-shelf

High performance

Low development costs

Low power

Short time to the market

Low cost (but only

in high volumes)

Reconfigurability

fpga design process 1
FPGA Design process (1)

Design and implement a simple unit permitting to speed up encryption with RC5-similar cipher with fixed key set on 8031 microcontroller. Unlike in the experiment 5, this time your unit has to be able to perform an encryption algorithm by itself, executing 32 rounds…..

Specification (Lab Experiments)

VHDL description (Your Source Files)

Library IEEE;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

entity RC5_core is

port(

clock, reset, encr_decr: in std_logic;

data_input: in std_logic_vector(31downto0);

data_output: out std_logic_vector(31downto0);

out_full: in std_logic;

key_input: in std_logic_vector(31downto0);

key_read: out std_logic;

);

end AES_core;

Functional simulation

Synthesis

Post-synthesis simulation

fpga design process 2
FPGA Design process (2)

Implementation

Timing simulation

Configuration

On chip testing

slide31

Logic Synthesis

VHDL description

Circuit netlist

architecture MLU_DATAFLOW of MLU is

signal A1:STD_LOGIC;

signal B1:STD_LOGIC;

signal Y1:STD_LOGIC;

signal MUX_0, MUX_1, MUX_2, MUX_3: STD_LOGIC;

begin

A1<=A when (NEG_A='0') else

not A;

B1<=B when (NEG_B='0') else

not B;

Y<=Y1 when (NEG_Y='0') else

not Y1;

MUX_0<=A1 and B1;

MUX_1<=A1 or B1;

MUX_2<=A1 xor B1;

MUX_3<=A1 xnor B1;

with (L1 & L0) select

Y1<=MUX_0 when "00",

MUX_1 when "01",

MUX_2 when "10",

MUX_3 when others;

end MLU_DATAFLOW;

top level asic digital design flow
Top Level ASIC Digital Design Flow

Design Inception

RTL Design

Synthesis

Macro Development

Place

+

Route

Physical Verification

Design Complete

slide38

CAD software available at GMU (1)

VHDL simulators

  • Aldec Active-HDL (under Windows)
  • available in the FPGA Lab, S&T II, room 203
  • student edition can be purchased on an individual
  • basis ($59.95 + S&H)
  • ModelSim Xilinx Edition III (under Windows)
  • available in the FPGA Lab, S&T II, room 203
  • limited version available for free for individual use
  • at home as a part of Xilinx WebPACK
slide39

CAD software available at GMU (2)

Tools used for logic synthesis

Xilinx FPGA synthesis

  • Synplicity Synplify Pro (under Windows)
    • available in the FPGA Lab, S&T II, room 203
  • Xilinx XST(under Windows)
  • available in the FPGA Lab, S&T II, room 203
  • available for free as a part of WebPACK
slide40

CAD software available at GMU (3)

Tools used for implementation (mapping, placing & routing)

in the Xilinx FPGA technology

  • Xilinx ISE (under Windows)
  • available in the FPGA Lab, S&T II, room 203
  • Xilinx WebPACK (under Windows)
  • limited version available for free for individual use
  • at home as a part of Xilinx WebPACK
slide41

CAD software available at GMU (4)

ASIC synthesis

  • Synopsys Design Compiler and PrimeTime (under Unix)
  • available from all PCs in the ECE educational labs
  • using an X-terminal emulator
  • available remotely from home using a fast Internet
  • connection
slide42

Xilinx FPGA Tools

Windows

Home for money

Home for free

Lab

ModelSim Xilinx Edition

Aldec Active HDL

Student Edition

Aldec Active HDL

Synplicity Synplify Pro

Xilinx ISE

Xilinx XST

Xilinx WebPACK

Xilinx XST

Xilinx WebPACK

slide43

Altera FPGA Tools

Windows

Home for free

Lab

Altera Quartus II

Altera Quartus II

slide44

ASIC Tools

Unix

Home for free

Lab

Synopsys Design Analyzer

remote access to cpe02.gmu.edu

Synopsys Design Analyzer

slide46

FPGA available on the XESS board

Xilinx Spartan 3,XC3S1000 FPGA

  • 1,000,000 equivalent logic
  • gates
  • 7680 CLB slices
  • 432 kbits of memory in block RAMs

Block RAMs

Programmable

Interconnects

Configurable Logic

Block slices (CLB slices)

slide48

FPGA available on the board

Xilinx Spartan 3,XC3S1500 FPGA

  • 1,500,000 equivalent logic
  • gates
  • 13,312 CLB slices
  • 576 kbits of memory in block RAMs

Block RAMs

Programmable

Interconnects

Configurable Logic

Block slices (CLB slices)

slide50

Digital system design technologies

coverage in the CpE & EE programs at GMU

ASICs

Microprocessors

FPGAs

Computer

Organization

ECE 445

ECE 447

ECE 431

Digital Circuit Design

Single Chip

Microcomputers

ECE 448

FPGA and ASIC Design with VHDL

ECE 545

Introductionto VHDL

ECE 511ECE 611

ECE 645

Microprocessors

Computer Arithmetic

Digital

Integrated

Circuits

Advanced

Microprocessors

ECE 586

ECE 681

VLSI Design

Automation

slide51

Why ECE 448 is a challenging course?

  • need to “relearn” VHDL
  • need to learn a lot of tools
  • need to perform practical experiments
  • time needed to complete experiments
slide52

ECE 448: Spring 2006

Student Survey Summary

slide53

Difficulties

  • finding time to do the labs - 15
  • learning VHDL – 2
  • getting used to software – 1
slide54

Average time spent per one experiment

9

8

7

6

5

4

3

2

1

0

2

6

8

10

15

20

24

30

32

48

slide55

Self-evaluation

3 – better than

expected

8 – worse than

expected

16 – as well as

expected

slide56

Why is this course worth taking?

  • VHDL for synthesis:
  • one of the most sought-after skills
  • knowledge of state-of-the-art tools used in the industry
  • knowledge of the modern FPGA & ASIC technologies
  • knowledge of state-of-the-art testing equipment
  • design portfolio that can be used during job interviews
  • unique knowledge and practical skills that make you
  • competitive at the job market