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Computer Architecture. Nguyen Thanh Kien Department of Computer Engineering Faculty of Information Technology Hanoi University of Technology. About. Author: Nguyen Thanh Kien Office: Department of Computer Engineering Faculty of Information Technology Hanoi University of Technology

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slide1

Computer Architecture

Nguyen Thanh KienDepartment of Computer EngineeringFaculty of Information TechnologyHanoi University of Technology

about
About
  • Author: Nguyen Thanh Kien
  • Office:

Department of Computer Engineering

Faculty of Information Technology

Hanoi University of Technology

  • Mobile: +84983 588 135
  • Email: kiennt-fit@mail.hut.edu.vn

thanhkien84@yahoo.com

content
Content

1. Introduction

2. Function Minimization Methods

3. Larger Combinational Systems

4. Sequential Systems

5. Hardware Design Languages

acknowledge
Acknowledge
  • The following materials are used as reference for this slide:
    • “Logic Circuits” slide, Dr. Trinh Van Loan.
    • Introduction to Logic Design, 2nd Ed, Alan B. Marcovitz, Mc. Graw Hill,2005
    • Foundation of Digital Logic Design, G.Langholz, A. Kandel, J. Mott, World Scientific, 1998
reference textbooks
Reference textbooks
  • Introduction to Logic Design, 2nd Ed,, Alan B, Marcovitz, Mc. Graw Hill,2005
  • Foundation of Digital Logic Design, G.Langholz, A. Kandel, J. Mott, World Scientific, 1998
grading policy
Grading policy
  • Homework: 20%
  • Lab work: 20%
  • Midterm: 30%
  • Final Exam (multichoice and writing): 30%
1 introduction
1. Introduction

1.1. Review of Number Systems

1.2. Switching Algebra and Logic Circuits

1 1 review of number systems
1.1. Review of Number Systems

1.1.1 Number Representation

1.1.2 Binary Addition

1.1.3 Signed Numbers

1.1.4 Binary Subtraction

1.1.5 Binary Coded Decimal (BCD)

1.1.6 Other Codes

1 1 review of number systems1
1.1. Review of Number Systems

1.1.1 Number Representation

1.1.2 Binary Addition

1.1.3 Signed Numbers

1.1.4 Binary Subtraction

1.1.5 Binary Coded Decimal (BCD)

1.1.6 Other Codes

1 1 1 number representation
1.1.1. Number Representation
  • Numbers are normally written using a positional number system:
    • Base/radix: b (the number of digits)
    • Digits: 0..(b-1)
      • 0 ≤ ai ≤ (b-1)
    • Binary: b=2, digits:0,1
    • Decimal: b=10, digits: 0,1,2,3,4,5,6,7,8,9
    • Octal: b=8, digits: 0,1,2,3,4,5,6,7
    • Hexadecimal: b=16, digits: 0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F
1 1 1 number representation1
1.1.1. Number Representation

11101.11(2) = 1x24+1x23+1x22+0x21+1x20+1x2-1+1x2-2= 29.75(10)

1 1 1 number representation2
1.1.1. Number Representation
  • Decimal:
    • b=10
    • Digits: 0,1,2,3,4,5,6,7,8,9
    • Eg:

539.45(10) = 5x102+3x101+9x100+4x10-1+5x10-2

ai = 0..9

1 1 1 number representation3
1.1.1. Number Representation
  • Binary:
    • b=2
    • Digits: 0,1
    • Eg:

1011.011(2) = 1x23 + 0x22 + 1x21 + 1x20 + 0x2-1 + 1x2-2 + 1x2-3

bit – binary digit

ai = 0,1

1 1 1 number representation4
1.1.1. Number Representation
  • Binary (cnt’)
    • n-bit binary number can represent which range?
      • an-1...a1a0 from 0 to 2n-1
    • MSB – Most Significant Bit
    • LSB – Least Significant Bit

0001 = 1 1001 = 9

0010 = 2 1010 = 10

0011 = 3 1011 = 11

0100 = 4 1100 = 12

0101 = 5 1101 = 13

0110 = 6 1110 = 14

0111 = 7 1111 = 15

1000 = 8

1 1 1 number representation5
1.1.1. Number Representation
  • Octal:
    • b=8
    • Digits: 0,1,2,3,4,5,6,7
    • Eg:

503.071(8) = 5x82 + 0x81 + 3x80 + 0x8-1 + 7x8-2 + 1x8-3

ai = 0..7

  • Hexadecimal:
    • b=16
    • Digits: 0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F
    • Eg:

503.071(16) = 5x162 + 0x161 + 3x160 + 0x16-1 + 7x16-2 + 1x16-3

ai = 0..F

convert from base b to base 10
Convert from base b to base 10
  • Base b to base 10 conversion
  • Eg:
    • 1010.11(2)=?
    • 1010.11(8)=?
    • A12(16)=?
convert from base 10 to base b
Convert from base 10 to base b
  • Base 10 to base b conversion
    • For integer part:
      • Divide integer part by b until the result is 0
      • Write remainders in reverse order to get the converted result.
    • For the odd part after “.”
      • Multiply by b until the result is 0
convert from base 10 to base 2
Convert from base 10 to base 2
  • The odd part after “.”
    • 0.625 x 2 = 1.25
    • 0.25 x 2 = 0.5
    • 0.5 x 2 = 1.0
  • Eg1: 6.625(10) = ?(2)
    • The integer part
  • Eg2: 20.75(10) = ?(2)

6.625(10) = 110.101(2)

convert from base 2 to base 2 n
Convert from base 2 to base 2n
  • Group from right to left n-bit groups and replace the equivalent values in base 2n
  • Eg:
  • 101011(2) = ?(8) 1010.110(2)=12.6(8)
  • 101011(2) = ?(16) 1010.110(2)=A.C(16)
convert from base 2 n to base 2
Convert from base 2n to base 2
  • Each digit in base 2n is replaced by n bit in base 2.
  • Eg:
  • 37A.B(16)=?(2)
convert from base i to base j
Convert from base i to base j
  • If both i and j are powers of 2, use base 2 as an intermediate base:
    • Eg: base 8  base 2  base 16
    • 735.37(8)=?(16)
  • Else, use base 10 as an intermediate base:
    • Eg: base 5  base 10  base 2
1 1 review of number systems2
1.1. Review of Number Systems

1.1.1 Number Representation

1.1.2 Binary Addition

1.1.3 Signed Numbers

1.1.4 Binary Subtraction

1.1.5 Binary Coded Decimal (BCD)

1.1.6 Other Codes

1 1 2 binary addition
1.1.2 Binary Addition
  • Binary long addition similar to decimal long addition.

decimalbinary carry 1100 11110

A 2565 10110

B 6754 11011

sum 9319 110001

Eg: 10101(2) + 11011(2) = ? (2)

1 1 2 binary addition1
1.1.2 Binary Addition
  • Overflow:
    • Occur when the result of addition is out of range of representation (the result can not be stored in the predefined number of bits)
    • In 8-bit computer, the result of addition of two binary numbers 10101010 and 11010011 is 9-bit binary number which can not be stored in 8-bit => overflow
1 1 2 binary addition2
1.1.2 Binary Addition
  • n-bit adder in computer:
1 1 review of number systems3
1.1. Review of Number Systems

1.1.1 Number Representation

1.1.2 Binary Addition

1.1.3 Signed Numbers

1.1.4 Binary Subtraction

1.1.5 Binary Coded Decimal (BCD)

1.1.6 Other Codes

1 1 3 signed numbers
1.1.3 Signed Numbers
  • Represent sign and amplitude
  • Use the most-left-bit to represent sign:
    • 0: positive, 1: negative
  • Eg: represent signed numbers using 4 bit:
    • +5 = 0101, -5 = 1101, -3 = 1011
    • Using 3 right bits to represent amplitude, we can represent from -7 to +7.
    • Drawbacks:
      • +0 = 0000, -0 = 1000 => complex when calculating

=> need an other representation

2 s complement representation
2’s complement representation
  • Most left bit is still sign bit
  • Positive and 0 numbers are expressed in usual binary format.
    • The largest number can be represented is 2n-1-1
    • n=8 => largest signed number: 28-1-1 = 127
  • Negative number a is stored as the binary equivalent of 2n-a in a n-bit system.
    • -3 is stored as 28-3=11111101 in a 8-bit system
    • The most negative number can be stored is -2n-1
2 s complement representation1
2’s complement representation
  • +10 = 0000 1010
  • - 10 = 28-10 = 1 0000 0000

– 0000 1010

1111 0110

- 10 = 1111 0110

  • +10 + (-10) = ?
2 s complement representation2
2’s complement representation
  • Procedure to find binary representation of negative number in 2’s complement:
    • Find the binary equivalent of the magnitude
    • Complement each bit (0=>1, 1=>0)
    • Add 1
  • Eg: find representation of -13 in 8-bit signed number system using 2’s complement:
      • Magnitude: 13 = 0000 1101
      • Complement: 1111 0010
      • Add 1: 1
      • -13 = 1111 0011

+

2 s complement representation3
2’s complement representation
  • Range of representation:
    • Use n bit to represent 2’s complement numbers
    • Range: -2n-1 => 2n-1-1
2 s complement representation4
2’s complement representation
  • To find the magnitude of a negative number:
    • Complement each bit
    • Add 1
  • Eg:
addition of signed numbers
Addition of signed numbers
  • The reason that 2’s complement is so popular is the simplicity of addition.
  • To add any two numbers, no matter what the sign of each is, we just do binary addition on their representation.
addition of signed numbers1
Addition of signed numbers
  • Overflow
    • Occur when?
    • Add two numbers of the opposite sign?
    • Add two positive numbers?
    • Add two negative numbers?

maybe

  • Overflow occurs when adding two numbers with the same sign and the result is in different sign
1 1 review of number systems4
1.1. Review of Number Systems

1.1.1 Number Representation

1.1.2 Binary Addition

1.1.3 Signed Numbers

1.1.4 Binary Subtraction

1.1.5 Binary Coded Decimal (BCD)

1.1.6 Other Codes

1 1 4 binary subtraction
1.1.4 Binary Subtraction
  • Find the 2’s complement of the second operand, then add.
  • a – b = a + (-b)
  • Eg: 7 – 5 = ?
1 1 review of number systems5
1.1. Review of Number Systems

1.1.1 Number Representation

1.1.2 Binary Addition

1.1.3 Signed Numbers

1.1.4 Binary Subtraction

1.1.5 Binary Coded Decimal (BCD)

1.1.6 Other Codes

binary coded decimal bcd
Binary-Coded Decimal - BCD
  • BCD:
    • Use four bits (a nibble) to represent each of the decimal digits 0 through 9.
    • Eg:

375 = 0011 0111 0101(BCD)

1 1 review of number systems6
1.1. Review of Number Systems

1.1.1 Number Representation

1.1.2 Binary Addition

1.1.3 Signed Numbers

1.1.4 Binary Subtraction

1.1.5 Binary Coded Decimal (BCD)

1.1.6 Other Codes

ascii
ASCII
  • American Standard Code for Information Interchange - ASCII
  • Use seven bits to represent various characters on the standard keyboard as well as a number of control signal
problems
Problems

1. Convert the following unsigned numbers:

  • 98.625(10)=?(2)
  • 11011.011(2)=?(10)
  • 6A1.1E(16)=?(8)

2. Represent the following signed numbers:

a. -74 in 8-bit signed 2’s complement.

b. -74 in 16-bit signed 2’s complement.

1 introduction1
1. Introduction

1.1. Review of Number Systems

1.2. Switching Algebra and Logic Circuits

1 2 switching algebra and logic circuits
1.2. Switching Algebra and Logic Circuits

1.2.1 Definition of Switching Algebra

1.2.2 Basic Properties of Switching Algebra

1.2.3 Manipulation of Algebraic Functions

1.2.4 Representations of Algebraic Functions

1.2.5 Implementation of Functions with AND, OR, NOT, NAND, NOR, XOR Gates

1 2 switching algebra and logic circuits1
1.2. Switching Algebra and Logic Circuits

1.2.1 Definition of Switching Algebra

1.2.2 Basic Properties of Switching Algebra

1.2.3 Manipulation of Algebraic Functions

1.2.3 Representations of Algebraic Functions

1.2.4 Implementation of Functions with AND, OR, NOT, NAND, NOR, XOR Gates

1 2 1 definition of switching algebra
1.2.1 Definition of Switching Algebra
  • Switching algebra is binary:
    • All variables and constant take on 0 or 1.
      • Light on/off, switch: up/down, voltage: low/high...
    • Quantities which are not naturally binary must be coded into binary format.
    • Three operators:
      • OR: a+b
      • AND: a.b
      • NOT: a’
1 2 switching algebra and logic circuits2
1.2. Switching Algebra and Logic Circuits

1.2.1 Definition of Switching Algebra

1.2.2 Basic Properties of Switching Algebra

1.2.3 Manipulation of Algebraic Functions

1.2.3 Representations of Algebraic Functions

1.2.4 Implementation of Functions with AND, OR, NOT, NAND, NOR, XOR Gates

basic properties of switching algebra
Basic Properties of Switching Algebra
  • P1: Commutative:
    • a + b = b + a a.b = b.a
  • P2: Associative:
    • a + (b + c) = (a + b) + c a.(b.c) = (a.b).c
  • P3:
    • a + 0 = a a . 1 = a
  • P4:
    • a + 1 = 1 a . 0 = 0
basic properties of switching algebra1
Basic Properties of Switching Algebra
  • P5:
    • a + a’ = 1 a . a’ = 0
  • P6: no coefficient and no exponent
    • a + a = a a . a = a
    • n.a=a (a)n=a
  • P7: complement
    • (a’)’ = a
  • P8: distributive:
    • a.(b+c) = a.b + a.c a + b.c = (a+b).(a+c)
basic properties of switching algebra2
Basic Properties of Switching Algebra
  • P9: adjacency
    • ab + ab’ = a (a+b)(a+b’)=a
  • P10:
    • a + a’b = a +b a(a’+b) = ab
  • P11: De Morgan
    • (a + b)’ = a’b’ (ab)’ = a’ + b’
  • P12: absorption
    • a + ab = a a(a+b) = a
basic properties of switching algebra3
Basic Properties of Switching Algebra
  • P13: redundant
    • ab+b’c+ac = ab+b’c
problems1
Problems

1. Prove the following equalities:

a. xy’+y=x+y

b. xy+xz’+yz=xy+x’z => prove it incorrect

c. x’y’z+yz+xz=z

d. (x+y)[x’(y’+z’)]’+x’y’+x’z’ = 1

1 2 switching algebra and logic circuits3
1.2. Switching Algebra and Logic Circuits

1.2.1 Definition of Switching Algebra

1.2.2 Basic Properties of Switching Algebra

1.2.3 Manipulation of Algebraic Functions

1.2.4 Representations of Algebraic Functions

1.2.5 Implementation of Functions with AND, OR, NOT, NAND, NOR, XOR Gates

manipulation of algebraic functions
Manipulation of Algebraic Functions
  • A literal:
    • Is the appearance of a variable or its complement
    • Eg: x and x’ are two different literals
    • Expression ab’+bc’d+a’d+e’ has 8 literals
  • A product term:
    • Is one or more literal connected by AND operators
    • Expression ab’+bc’d+a’d+e’has 4 product terms
    • Note: A single literal is also a product term
manipulation of algebraic functions1
Manipulation of Algebraic Functions
  • A standard product term - minterm:
    • Is a product term which includes every variable of the function, either uncomplemented or complemented.
    • Eg: for a function of four variables a,b,c,d:
      • the product term a’bc’d is a standard product term
      • the product term a’bd’ is not
slide58

Manipulation of Algebraic Functions

  • A sum of product - SOP:
    • Is one or more product terms connected by OR operators
    • Eg:
      • ab’c+abc’+a’c+a’
      • d
  • A canonical sum – sum of standard product term
    • Is a sum of products expression where all terms are standard product terms.
    • Eg: A function of three variables a,b,c:
      • ab’c + abc’ + abc is a canonical sum
      • ab’c + abc’ + a is not
slide59

Manipulation of Algebraic Functions

  • A minimum sum of products:
    • Is one of those SOP expression for a function that has the fewest number of product terms.
    • If there is more than one expression with fewest number of terms, then minimum is defined as one or more of those expressions with the fewest number of literals.
    • Eg:
      • F1(x,y,z) = x’yz’+x’yz+ xy’z’+xy’z+xyz
      • F2(x,y,z) = x’y+xy’+xyz
      • F3(x,y,z) = x’y+xy’+xz
      • F4(x,y,z) = x’y+xy’+yz

F3,F4 are minimum SOP of F1

slide60

Manipulation of Algebraic Functions

  • A sum term:
    • Is one or more literals connected by OR operators
    • Eg:
      • a + b’ + c’
      • b’
  • A standard sum term - maxterm:
    • Is a sum term that includes each variable of the problem, either uncomplemented or complemented
    • Eg: For a function of four variables x,y,z,t
      • x+y+z’+t’ is a maxterm
      • x+y+t’ is not
slide61

Manipulation of Algebraic Functions

  • A product of sum – POS:
    • Is one or more sum terms connected by AND
    • Eg:
      • (w+x’+y’)(w+y+z’)(w+x+z)
      • w
  • A canonical product – product of standard sum terms:
    • Is a product of sum term where all sum terms are standard
slide62

Manipulation of Algebraic Functions

  • A minimum POS is defined the same way as SOP:
    • fewest number of terms
    • the same number of terms => fewest number of literals
canonical forms
Canonical forms
  • Three-variable minterm and Maxterm
canonical forms1
Canonical forms
  • Properties of minterm/Maxterm:
    • mimj=0 if i≠j

=mi if i=j

    • Mi+Mj=1 if i≠j

= Mi if i=j

    • mi=Mi’ and Mi=mi’ for every i
canonical forms2
Canonical forms
  • An algebraic expression of a Boolean function can be derived from a given true table in two ways:
    • By summing (ORing) those minterm for which the function takes a value 1.
    • By multiplying (ANDing) those maxterm for which the function takes a value 0.
canonical forms3
Canonical forms

f(x2,x1,x0)=m1+m4+m5+m6+m7

=Σ(1,4,5,6,7)

Canonical sum-of-products (SOP)

f(x2,x1,x0)=M0M2M3

= Π(0,2,3)

Canonical product-of-sums (POS)

f a b c abc a b
F(a,b,c)= abc’+a’b’
  • F(a,b,c)=m0+m1+m6
    • ∑(0,1,6)
1 2 switching algebra and logic circuits4
1.2. Switching Algebra and Logic Circuits

1.2.1 Definition of Switching Algebra

1.2.2 Basic Properties of Switching Algebra

1.2.3 Manipulation of Algebraic Functions

1.2.4 Representations of Algebraic Functions

1.2.5 Implementation of Functions with AND, OR, NOT, NAND, NOR, XOR Gates

1 2 3 representations of algebraic functions
1.2.3 Representations of Algebraic Functions
  • Truth table
  • Venn diagram
  • Karnaugh map
truth table
Truth table
  • List all the possible binary combinations of the independent variables and display the corresponding binary values of dependant variables.
truth table1
Truth table
  • n independent variables and m dependant functions:

2n rows

n+m columns

2 dependent

functions

3 independent

variables

23 rows

venn diagram
Venn diagram
  • Venn diagram using ‘space’ to present logic
  • F(A,B)=A.B

F(A,B)=C.not(B)

venn diagram1
Venn diagram

A

A

A.B

A+B

A+B

A.B

karnaugh map
Karnaugh map
  • A Karnaugh map is a graphical method for representing the true table of a Boolean function.
  • K-map may be used for any variables number, but often at most six.
karnaugh map k map
Karnaugh map (K-map)
  • If variables number is n => 2n cells in K-map.
  • 2n cells are arranged in logical pattern for minimization purpose.
two variable k map
Two-variable K-map
  • F(A,B)

B

0 1

A

0 1

A

B

0

1

0

1

two variable k map1
Two-variable K-map
  • F(A,B) = AB

B

0 1

A

0

1

three variable k map1
Three-variable K-map
  • F(x,y,z) = xyz + yz’ + x
four variable k map1
Four-variable K-map
  • F(A,B,C,D) = AB + CD’ + BCD
five variable k map
Five-variable K-map

E

0

1

CD

CD

00 01 11 10

00 01 11 10

AB

AB

00

01

11

10

1 1

1 1

1 1

00

01

11

10

1 1

1 1

1 1

5 variables Karnaugh Map consists of two

4 variables Karnaugh Map connected up/down.

six variable k map
Six-variable K-map

F

0

1

E

CD

CD

00 01 11 10

00 01 11 10

AB

AB

00

01

11

10

1 1

1 1

1 1

00

01

11

10

1 1

1 1

1 1

0

CD

CD

00 01 11 10

00 01 11 10

AB

AB

00

01

11

10

1 1

1 1

1 1

00

01

11

10

1 1

1 1

1 1

1

karnaugh map with don t care
Karnaugh map with don’t care

don’tcare ~ input conditions that not occur

1 2 switching algebra and logic circuits5
1.2. Switching Algebra and Logic Circuits

1.2.1 Definition of Switching Algebra

1.2.2 Basic Properties of Switching Algebra

1.2.3 Manipulation of Algebraic Functions

1.2.3 Representations of Algebraic Functions

1.2.4 Implementation of Functions with AND, OR, NOT, NAND, NOR, XOR Gates

basic logic gates1
Basic logic gates

NAND NOR XOR

implementation of functions with and or
Implementation of Functions with AND, OR
  • Assume all inputs are available in uncomplemented and complemented

F2 = x’y+xy’+xz

F1 = x’yz’+x’yz+xy’z’+xy’z+xyz

implementation of functions with and or not
Implementation of Functions with AND, OR, NOT
  • Complemented inputs can be produced using inverters NOT:

X

Y

F

Z

multilevel circuits
Multilevel circuits
  • A circuit is called n-level circuit if the maximum number of gates through which one signal must pass from input to output

two-level circuit

three-level circuit

implementation of functions with nand
Implementation of Functions with NAND
  • Using equivalent change steps, every expression can be represented using only NAND gates.

OR

A

NOT

B

A

A.B

(A’.B’)’

=A+B

B

AND

implementation of functions with nand1
Implementation of Functions with NAND
  • Represent the following expression using only NAND:
    • F(a,b,c) = ab + bc’ + b’

=

implementation of functions with nor
Implementation of Functions with NOR
  • Using equivalent change steps, every expression can be represented using only NOR gates.
implementation of functions with nor1
Implementation of Functions with NOR
  • Represent the following expression using only NOR:
    • F(a,b,c) = ab + bc’ + b’
slide95
Chapter 2.

Function Minimization Methods

2 function minimization methods
2. Function Minimization Methods

2.1 Algebraic Method

2.2 The Karnaugh Map Method

2.3 Quine-McCluskey Method

2 function minimization methods1
2. Function Minimization Methods
  • What is minimization?
    • Number of operands is minimal and number of literal in each operand is minimal
  • Why minimization needed?
    • Minimize electronic components used to construct the circuit to implement that expression
2 function minimization methods2
2. Function Minimization Methods

2.1 Algebraic Method

2.2 The Karnaugh Map Method

2.3 Quine-McCluskey Method

2 1 algebraic method
2.1 Algebraic Method
  • Use algebraic properties to minimize expressions
  • Drawback:
    • Heuristic, depending on experience – no formal method/procedure
    • Manually
    • Not sure whether the last expression is minimal or not
2 1 algebraic method1
2.1 Algebraic Method
  • Eg: Minimize these expressions using algebraic method:
    • F0(x,y,z)=xyz+x’yz+xy’z+xyz’
    • F1(a,b,c,d)=ab+abc+a’cd+a’c’d+a’bcd’
    • F2(A,B,C,D)=
    • F3(x,y,z)=(x+y)(x+y+z’)+y’
    • F4(a,b,c,d)=(a+b’+c)(a+c’)(a’+b’+c)(a+c+d)
2 2 the karnaugh map method
2.2 The Karnaugh Map Method

1. Minimum Sum of Product Expressions Using the Karnaugh Map

2. Don’t Cares

3. Product of Sums

4. Minimum Cost Gate Implementation

5. Five- and Six-Variable Maps

6. Multiple Output Problems

implicant prime implicant
Implicant, Prime Implicant
  • An implicant of a function is a product term that can be used in a SOP

Implicants of F

Minterm Groups of 2 Groups of 4

A’B’C’D’ A’CD AB

A’B’CD BCD

A’BCD ABC’

ABC’D’ ABD

ABCD’ ABC

ABC’D ABD’

ABCD

implicant prime implicant1
Implicant, Prime Implicant
  • A prime Implicant is an implicant which can not be contained in any other implicants.
essential prime implicant
Essential Prime Implicant
  • Essential PI is a PI which contains at least one minterm which is not contained in other PI.

minterm 0 is only contained in PI B’D’

minterm 5 is only contained in PI BD

=> BD & B’D’ are two Essential PI

2 2 1 minimum sum of product expressions
2.2.1 Minimum Sum of Product Expressions
  • Rules to minimize using K-map:
    • Rule 1: Fill K-map cells with corresponding values
    • Rule 2: Group adjacent cells whose values are 1. Number of cells is 2n.
    • Rule 3: Each group will be a part of result. Variables in each group will be excluded: 2n cells => exclude n variables.
2 2 1 minimum sum of product expressions1
2.2.1 Minimum Sum of Product Expressions
  • Step 2: Group adjacent cells whose values are 1. Number of cells is 2n.
2 2 1 minimum sum of product expressions2
2.2.1 Minimum Sum of Product Expressions
  • Step 3: Each group will be a part of result. Variables in each group will be excluded: 2n cells => exclude n variables.

21 cells => eliminate 1 variable

F(A,B,C,D) = A’BC’ + AC

22 cells => eliminate 2 variables

2 2 1 minimum sum of product expressions3
2.2.1 Minimum Sum of Product Expressions
  • Example 1:

Minimize these functions using K-map:

    • a. F(A,B,C,D) = R(0,2,5,6,9,11,13,14)
    • b. F(A,B,C,D) = R(1,3,5,8,9,13,14,15)
    • c. F(A,B,C,D) = R(2,4,5,6,7,9,12,13)
    • d. F(A,B,C,D)= R(1,3,4,5,7,9,13,14,15)
slide109
a. F(A,B,C,D) = R(0,2,5,6,9,11,13,14)

= BC’D + AB’D + BCD’ + A’B’D’

2 2 the karnaugh map
2.2 The Karnaugh Map

1. Minimum Sum of Product Expressions Using the Karnaugh Map

2. Don’t Cares

3. Product of Sums

4. Minimum Cost Gate Implementation

5. Five- and Six-Variable Maps

6. Multiple Output Problems

2 2 2 don t care
2.2.2 Don’t care
  • If the function has don’t care values in cells:
    • Cells with don’t care values

can be grouped with ‘1’ cells

    • Do not group only don’t

care cells in one group.

examples
Examples:

F(a,b,c,d)=R(1,3,5,7,12,13)

don’t care (0,4,10,15)

2 function minimization methods3
2. Function Minimization Methods

2.1 Algebraic Method

2.2 The Karnaugh Map Method

2.3 Quine-McCluskey Method

2 3 quine mccluskey method
2.3 Quine-McCluskey Method

1. Quine-McCluskey Method for One Output

2. Iterated Consensus for One Output

3. Prime Implicant Tables for One Output

4. Quine-McCluskey for Multiple Output Problems

5. Iterated Consensus for Multiple Output Problems

6. Prime Implicant Tables for Multiple Output Problems

2 3 quine mcluskey method
2.3. Quine-Mcluskey method

Karnaugh map cannot handle more than 6 variables.

Quine-McCluskey method has no limitation with number of

variables, and is suitable for computer algorithm.

ABC+ABC+ABC+ABC+ABC

C

010

110

111

100

101

AB

0 1

00

01 1

11 1 1

10 1 1

*10

11*

1*0

1*1

10*

1**

find a pair of numbers of 1 bit difference

quine mcluskey procedure
Quine-Mcluskey Procedure
  • 1: Represent minterms in binary numbers
  • 2: Group each minterm by the number of ‘1’ appearance
  • 3: Make set of 1 bit different numbers between neighboring group
      • write the difference within parenthesis
      • mark * to the number which is not included in a set
  • 4: Make set of 1 bit different sets with the same number in a parenthesis
      • append the difference to parenthesis
      • mark + to the set which is not included in a set
  • 5: Iterate these step until all the generated set is marked *
  • 6: Select prime implicants
  • 7: Convert to logic variable
s1 represent minterms in binary numbers
S1. Represent minterms in binary numbers

f = ABCDEF+ABCDEF+ABCDEF+ABCDEF+ABCDEF

+ABCDEF+ABCDEF +ABCDEF+ABCDEF+ABCDEF

f(A,B,C,D,E,F)=Σ(0,2,6,7,14,8,41,12,15,10)

f = 000000+000010+000110+000111+001110

+001000+101001+001100+001111+001010

s2 grouping
S2. Grouping

f = 000000+000010+000110+000111+001110

+001000+101001+001100+001111+001010

group each term by the appearance of 1

group 3

group 4

group 0

group 1

group 2

once

twice

three times

four times

no times

000110

001100

001010

000111

001110

101001

000000

000010

001000

001111

s3 s4 making set 1
S3 & S4. Making set (1)

group 0

000000 0

000010 2

001000 8

000110 6

001010 10

001100 12

000111 7

001110 14

101001 41

001111 15

0,2 (2)

0,8 (8)

find a pair of 1 bit difference

between neighboring group

write difference within ( )

group 1

2,6(4)

2,10(8)

8,10(2)

8,12(4)

group 2

mark

to the number

not included in any set

6,7(1)

6,14(8)

10,14(4)

12,14(2)

group 3

group 4

7,15(8)

14,15(1)

s3 s4 making set 2
S3 & S4. Making set (2)

find a pair of 1 bit different sets

with the same value in ( )

between neighboring group

append difference within ( )

0,2 (2)

0,8 (8)

0,2,8,10(2,8)

2,6(4)

2,10(8)

8,10(2)

8,12(4)

2,6,10,14(4,8)

8,10,12,14(2,4)

Each pair appears in duplicate

mark to the set

not involved

in the next level set

6,7(1)

6,14(8)

10,14(4)

12,14(2)

6,7,14,15(1,8)

when all the set is marked

finish

7,15(8)

14,15(1)

s6 selecting prime implicants 1
S6. Selecting Prime Implicants (1)

minterms (given at first)

Prime implicant( marked)

0 2 6 7 8 10 12 14 15 41

x

41

0,2,8,10(2,8)

2,6,10,14(4,8)

8,10,12,14(2,4)

6,7,14,15(1,8)

x

x

x

x

x

x

x

x

x

x

x

x

x

x

x

x

write x into the position where minterm is included

in the prime implicant

inevitable

implicant

If only one x in a column, then the row is inevitable implicant

s6 selecting prime implicants 2
S6. Selecting Prime Implicants (2)

mini term

0 2 6 7 8 10 12 14 15 41

x

prime implicants

41

0,2,8,10(2,8)

2,6,10,14(4,8)

8,10,12,14(2,4)

6,7,14,15(1,8)

x

x

x

x

x

x

x

x

x

x

x

x

x

x

x

x

mark minterms involved in the

inevitable implicants

inevitable

implicants

s7 c onversion to logic variables
S7. Conversion to logic variables

41

101001

ABCDEF

000000

000010

001000

001010

ABDF

0,2,8,10(2,8)

F=ABCDEF

+ABDF

+ABCF

+ABDE

001000

001010

001100

001110

8,10,12,14(2,4)

ABCF

000110

000111

001110

001111

6,7,14,15(1,8)

ABDE

examples1
Examples:
  • Minimize the following functions using Quine-Mcluskey method:
    • a.
    • b. F(a,b,c,d,e,f) =

∑(17,21,25,29, 44,45,46,47,49,52,53,54,55,47,61)

quine mcluskey method w ith don t care
Quine-Mcluskey method with don’t care
  • 1: Represent logic function in sum of mini terms ==>A
  • 2: Represent don’t care in sum of mini terms ==>B
  • 3: If there exist duplication in A and B, remove from A
  • 4: Apply Quine-McCluskey method for A and B
  • 5: Be careful not to include B in selecting prime implicants
quine mcluskey method w ith don t care1
Quine-Mcluskey method with don’t care

f=ABCD+BCD+ACD+ABCD+ABCD

don’t care AD

mini term

ABCD

decimal

first comparison

second comparison

0,1(1)

0,2(2)

1,3(2)

1,5(4)

2,3(1)

3,7(4)

3,11(8)

5,7(2)

5,13(8)

7,15(8)

11,15(4)

13,15(2)

0

1

2

3

5

7

11

13

15

0000

0001

0010

0011

0101

0111

1011

1101

1111

0,1,2,3(1,2)

1,3,5,7(2,4)

3,7,11,15(4,8)

5,7,13,15(2,8)

quine mcluskey method w ith don t care2
Quine-Mcluskey method with don’t care

0 2 11 13 15

ABCD

00**

0,1,2,3(1,2)

x

x

0**1

1,3,5,7(2,4)

x

x

**11

3,7,11,15(4,8)

x

x

*1*1

5,7,13,15(2,8)

f=AB+CD+BD

slide129
Chapter 3.

Larger Combinational Systems

introduction
Introduction
  • Logic circuits are divided into two classes:
    • Combinational logic circuits
      • Output signals only depend on current input signals
      • Memoryless circuits
    • Sequential logic circuits
      • Output signals not only depend on current input signals, but also depend on those input signals in the past
      • Memory circuits
3 larger combinational systems
3. Larger Combinational Systems
  • 3.1 Delay in Combinational Logic Circuits
  • 3.2 Adders and Other Arithmetic Circuits
  • 3.3 Decoders
  • 3.4 Encoders
  • 3.5 Multiplexers
  • 3.6 Demultiplexers
  • 3.7 Three-State Gates
  • 3.8 Gate Arrays-ROMs, PLAs and PALs
  • 3.9 Larger Examples
3 1 delay in combinational logic circuits
3.1 Delay in Combinational Logic Circuits
  • Delay through logic gates
    • When the input to a gate changes, the output of that gate doesn’t change immediately; but there is a small delay Δ.
    • The output is stable after the longest delay path
3 larger combinational systems1
3. Larger Combinational Systems
  • 3.1 Delay in Combinational Logic Circuits
  • 3.2 Adders and Other Arithmetic Circuits
  • 3.3 Decoders
  • 3.4 Encoders
  • 3.5 Multiplexers
  • 3.6 Demultiplexers
  • 3.7 Three-State Gates
  • 3.8 Gate Arrays-ROMs, PLAs and PALs
  • 3.9 Larger Examples
half adder

a

b

r

(Result)

r

a

b

0

0

0

0

0

1

1

0

1

0

1

0

1

1

0

1

HA

=1

a

b

&

r

Half Adder

=a  b

r = ab

(Carry-out)

Half Adder

addition of two n bit numbers
Addition of two n-bit numbers

r3

r2

r1

r0

A =

a3

a2

a1

a0

+B =

b3

b2

b1

b0

r43

r3 2

r2 1

r10

4 3

2

1

0

Summation

full adder

FA

ai

ri

bi

ai

bi

ri

i

ri+1

i

ri+1

0

0

0

0

0

0

0

1

1

0

0

1

0

1

0

0

1

1

0

1

1

0

0

1

0

1

0

1

0

1

1

1

0

0

1

1

1

1

1

1

Full Adder

i

ri+1

i = ai bi ri

ri+1 = ai bi + ri (ai bi)

combinational logic circuit design procedure
Combinational logic circuit design procedure
  • Problems: design a combinational logic circuit to do smth.
  • Design procedure:
    • S1: Find inputs, outputs.
    • S2: Construct truth table
    • S3: For each output, using K-map to minimize from truth table.
    • S4: Draw the circuit.
example 1
Example 1
  • Problem: Design a combinational logic circuit to implement this operation: M=N+3, N is 3-bit binary number, the number of bit of M is selected properly.
  • Solution:
    • S1: three inputs: n2n1n0

four outputs: m3m2m1m0

example 11
Example 1
  • S1: three inputs: n2n1n0

four outputs: m3m2m1m0

  • S2: truth table

m3

m2

m1

m0

n2

n1

n0

  • S3:

m3 = n2n0 + n2n1

example 2
Example 2
  • Problem: design a combinational logic circuit to calculate square of a 2-bit binary number.
  • Solution:
    • Step1: find inputs, outputs
      • Inputs: a1,a0
      • Outputs: b3,b2,b1,b0

Ex2

example 21
Example 2
  • Step 2: truth table
  • Step3: using K-map to minimize outputs
    • b3 = a1.a0 b1 = 0
    • b2 = a1.a0’ b0 = a0
example 22
Example 2
  • Step 4: Draw circuit
    • b3 = a1.a0 b1 = 0
    • b2 = a1.a0’ b0 = a0
full adder1

ri

ai

bi

=1

=1

i

&

&

1

ri+1

Full Adder
full adder2
Full Adder

ri

ai

bi

HA

HA

=1

=1

i

&

&

1

ri+1

n bit adder

a1 b1

a0 b0

an-1 bn-1

an-2 bn-2

r1

r0= 0

rn-1

rn-2

FA

FA

FA

FA

rn

r2

n

1

0

n-1

n-2

n-bit Adder
  • Serial n-bit adder

A = an-1an-2...a1a0 , B = bn-1bn-2...b1b0

Delay = n x Δ?

n bit adder1

r1

G0

 1

P0

r0

1

2

&

&

n-bit Adder
  • Parallel n-bit adder:

ri+1 = aibi + ri(ai bi)

ri+1 = Gi + ri Pi

Pi = ai bi and Gi = aibi

r1 = G0 + r0P0

r2

G1

 1

G0

P1

r2 = G1 + G0P1 + r0P0P1

&

P0

r0

2

1

parallel 4 bit addition

a3 b3 a2 b2 a1 b1 a0 b0

r0

Calculate Pi and Gi

P3 G3 P2 G2 P1 G1 P0 G0

Carry calculation

r0

r3

r2

r1

r4

a3 b3

a0 b0

a2 b2

a1 b1

Sum calculation

r4 = 43210

Parallel 4-bit addition
subtractor
Subtractor
  • To subtract a-b, simply add a to 2’s complement of b.
  • Second choice:

Half Subtractor => Full Subtractor => n-bit Subtractor

subtractor1
Subtractor
  • Subtractor by using 2’s complement

B3

B2

B1

B0

A3

A2

A1

A0

A

B

A

A

A

B

B

B

C4

FA

FA

FA

FA

C+

C+

C+

C+

C

1

C

C

C

C3

C2

C1

S

S

S

S

S1

S0

S3

S2

adder and subtractor
Adder and Subtractor

B1

B0

A3

B3

B2

A1

A0

A2

MPX

MPX

MPX

MPX

sel

A

B

A

A

A

B

B

B

C4

FA

FA

FA

FA

C+

C+

C+

C+

C

C

C

C

C3

C2

C1

S

S

S

S

S3

S2

S1

S0

3 larger combinational systems2
3. Larger Combinational Systems
  • 3.1 Delay in Combinational Logic Circuits
  • 3.2 Adders and Other Arithmetic Circuits
  • 3.3 Decoders
  • 3.4 Encoders
  • 3.5 Multiplexers
  • 3.6 Demultiplexers
  • 3.7 Three-State Gates
  • 3.8 Gate Arrays-ROMs, PLAs and PALs
  • 3.9 Larger Examples
decoder
Decoder
  • An nxm decoder is a combinational circuit that converts binary information from n input lines to m output lines, where m≤2n.
    • m = 2n => complete decoder
  • Fundamental property: only one output is 1 for any given input combination.
decoder1
Decoder
  • Complete decoders: m=2n

Eg:

+ 3 bit inputs x1,x2,x3.

+ 8 bit outputs Y0,Y1…Y7

design 3x8 decoder
Design 3x8 decoder

En

if (En=0)

Disable or D0...D7=0

else if (En=1)

Function as a 3x8 decoder

bcd to decimal decoder

N

A

B

C

D

Y0

Y1

..

Y9

0

0

0

0

0

1

0

..

0

1

0

0

0

1

0

1

..

0

2

0

0

1

0

0

0

..

0

3

0

0

1

1

0

0

..

0

4

0

1

0

0

0

0

..

0

5

0

1

0

1

0

0

..

0

6

0

1

1

0

0

0

..

0

7

0

1

1

1

0

0

..

0

8

1

0

0

0

0

0

..

0

9

1

0

0

1

0

0

.

1

BCD-to-decimal decoder

Y0

Y1

Yi

Y9

BCD

to

decimal

Decoder

A

B

C

D

:

:

decoder2
Decoder
  • 4x16 decoder using two 3x8 decoders
decoder implementation of arbitrary functions
Decoder implementation of arbitrary functions

F1(x1,x2,x3,x4)=Σ(0,1,3,8,12)

bcd to 7segment decoder

a

g

b

f

c

e

d

BCD-to-7segment decoder

Each segment is a Light

Emitting Diode (LED)

3 larger combinational systems3
3. Larger Combinational Systems
  • 3.1 Delay in Combinational Logic Circuits
  • 3.2 Adders and Other Arithmetic Circuits
  • 3.3 Decoders
  • 3.4 Encoders
  • 3.5 Multiplexers
  • 3.6 Demultiplexers
  • 3.7 Three-State Gates
  • 3.8 Gate Arrays-ROMs, PLAs and PALs
  • 3.9 Larger Examples
encoder
Encoder
  • An encoder is a circuit that performs the function of a decoder in reverse.
  • An mxn encoder has m inputs, n outputs where m≤2n. The outputs generate the binary codes corresponding to m inputs.
  • For example: encoder for PC’s keyboard

Key <=> Character <=> Key code

102 keys, 8 bit ASCII

keyboard encoder

‘1’

P1

1

2

i Encoder

9

A

B

C

D

P2

Pi

N=i

P9

Keyboard encoder
  • 9 keys
  • 4-bit key code.
keyboard encoder1
Keyboard encoder

A = 1 if (N=8) or (N=9)

B = 1 if (N=4) or (N=5) or (N=6)

or (N=7)

C = 1 if (N=2) or (N=3) or (N=6)

or (N=7)

D = 1 if (N=1) or (N=3) or (N=5)

or (N=7) or (N=9)

keyboard encoder2

N=1

 1

D

N=2

N=3

 1

C

N=4

N=5

N=6

 1

B

N=7

 1

N=8

A

N=9

Keyboard encoder
3 larger combinational systems4
3. Larger Combinational Systems
  • 3.1 Delay in Combinational Logic Circuits
  • 3.2 Adders and Other Arithmetic Circuits
  • 3.3 Decoders
  • 3.4 Encoders
  • 3.5 Multiplexors
  • 3.6 Demultiplexors
  • 3.7 Three-State Gates
  • 3.8 Gate Arrays-ROMs, PLAs and PALs
  • 3.9 Larger Examples
multiplexor

MUX 4-1

MUX 2-1

X0

X0

X1

Y

Y

X2

X1

X3

C0

C0

C1

C1

C0

Y

C0

Y

0

0

X0

0

X0

0

1

X1

1

0

X2

1

X1

1

1

X3

Multiplexor
  • Multiplexor has one output and more than one input.
  • Function: select one of input for output

control inputs

2 to 1 multiplexor

C0

X1

X0

Y

0

0

0

0

C0

Y

X0

0

0

1

1

Y

0

X0

0

1

0

0

X1

1

X1

0

1

1

1

C0

1

0

0

0

1

0

1

0

1

1

0

1

1

1

1

1

2-to-1 Multiplexor

MUX 2-1

4 to 1 multiplexor
4-to-1 Multiplexor

Y = s1’s0’I0 + s1’s0I1 +s1s0’I2+ s1s0I3

application of multiplexor

Source 1

Source 2

B = b3 b2 b1 b0

A = a3 a2 a1 a0

C0

Y3

Y1

Y2

Y0

Receiver

Application of multiplexor
  • Select source
application of multiplexor1

C0

a0

1

a1

0

Y

t

C1

a2

1

a3

0

t

C0

Y

a0

a1

a2

a3

C1

t

Application of multiplexor
  • Convert parallel-serial

A

application of multiplexor2
Application of multiplexor
  • Implementation of arbitrary functions:

x0

x1

x2

x3

C1 C0

f(0,0)

f(0,1)

f(1,0)

f(1,1)

Y = f(A,B)

Inputs to select function

A

B

Variables

example
Example
  • F(A,B) = A’B + AB’

x0

x1

x2

x3

C1 C0

0

1

1

0

Y = f(A,B)

Inputs to select function

A

B

Variables

3 larger combinational systems5
3. Larger Combinational Systems
  • 3.1 Delay in Combinational Logic Circuits
  • 3.2 Adders and Other Arithmetic Circuits
  • 3.3 Decoders
  • 3.4 Encoders and Priority Encoders
  • 3.5 Multiplexers
  • 3.6 Demultiplexers
  • 3.7 Three-State Gates
  • 3.8 Gate Arrays-ROMs, PLAs and PALs
  • 3.9 Larger Examples
demultiplexor

S0

S1

E

C0

Demultiplexor
  • Demultiplexor has one input and more than one output
  • Function: select one of outputs for input

DeMUX 1-2

3 larger combinational systems6
3. Larger Combinational Systems
  • 3.1 Delay in Combinational Logic Circuits
  • 3.2 Adders and Other Arithmetic Circuits
  • 3.3 Decoders
  • 3.4 Encoders and Priority Encoders
  • 3.5 Multiplexers
  • 3.6 Demultiplexers
  • 3.7 Three-State Gates
  • 3.8 Gate Arrays-ROMs, PLAs and PALs
  • 3.9 Larger Examples
3 7 three state gates tristate
3.7 Three-State Gates (Tristate)
  • Three state gates exhibit three states instead of two states. The three states are:
    • High : 1
    • Low : 0
    • High impedance : z
      • In this state the output is disconnected which is equal to open circuit. In the other words in that state circuit has no logic significant. We can have AND or NAND three-state gates but the most common is three-state buffer gate
3 7 three state gates tristate1
3.7 Three-State Gates (Tristate)
  • We may use conventional gates such as AND or NAND as three-state gates but the most common is three-state buffer gate.
  • Note that buffer produces transfer function and can be used for power amplification. Three state buffer has extra input control line entering the bottom of the gate symbol (see next slide)
three state buffer
Three-State buffer
  • Three-state buffer
  • C A Y
  • ----------------------
  • 0 0 z
  • 0 1 z
  • 0 0
  • 1 1 1
application of three state buffer
Application of three-state buffer
  • Three-state buffers can be used to implement

multiplexer

3 larger combinational systems7
3. Larger Combinational Systems
  • 3.1 Delay in Combinational Logic Circuits
  • 3.2 Adders and Other Arithmetic Circuits
  • 3.3 Decoders
  • 3.4 Encoders and Priority Encoders
  • 3.5 Multiplexers
  • 3.6 Demultiplexers
  • 3.7 Three-State Gates
  • 3.8 Gate Arrays - ROMs, PLAs and PALs
  • 3.9 Larger Examples
pla programmable logic arrays

• • •

inputs

ORarray

ANDarray

productterms

outputs

• • •

PLA - Programmable logic arrays
  • Pre-fabricated building block of many AND/OR gates
    • actually NOR or NAND
    • "personalized" by making or breaking connections among the gates
    • programmable array block diagram for sum of products form

A B C Z1 Z2m0 0 0 0 0 1m1 0 0 1 0 0m2 0 1 0 1 1m3 0 1 1 0 0m4 1 0 0 0 1m5 1 0 1 1 0m6 1 1 0 1 1m7 1 1 1 1 0

before programming
Before programming
  • All possible connections are available before "programming"
    • in reality, all AND and OR gates are NANDs
after programming

B

C

A

AB

B'C

AC'

B'C'

A

F0

F1

F2

F3

After programming
  • Unwanted connections are "blown"
    • fuse (normally connected, break unwanted ones)
    • anti-fuse (normally disconnected, make wanted connections)
pla example

A

B

C

A'B'C'

A'B'C

A'BC'

A'BC

AB'C'

AB'C

ABC'

ABC

A B C F1 F2 F3 F4 F5 F6

0 0 0 0 0 1 1 0 0

0 0 1 0 1 0 1 1 1

0 1 0 0 1 0 1 1 1

0 1 1 0 1 0 1 0 0

1 0 0 0 1 0 1 1 1

1 0 1 0 1 0 1 0 0

1 1 0 0 1 0 1 0 0

1 1 1 1 1 0 0 1 1

F1

F2

F3

F4

F5

F6

PLA example
  • Multiple functions of A, B, C
    • F1 = A B C
    • F2 = A + B + C
    • F3 = A' B' C'
    • F4 = A' + B' + C'
    • F5 = A xor B xor C
    • F6 = A xnor B xnor C

full decoder as for memory address

bits stored in memory

pals and plas
PALs and PLAs
  • Programmable logic array (PLA)
    • what we've seen so far
    • unconstrained fully-general AND and OR arrays
  • Programmable array logic (PAL)
    • constrained topology of the OR array
    • innovation by Monolithic Memories
    • faster and smaller OR plane

a given column of the OR array has access to only a subset of the possible product terms

rom read only memories

1

1

1

1

ROM – Read Only Memories
  • Two dimensional array of 1s and 0s
    • entry (row) is called a "word"
    • width of row = word-size
    • index is called an "address"
    • address is input
    • selected word is output

word lines (only one is active – decoder is just right for this)

n

2 -1

Example:

10 address x 8 data ROM

210 words x 8 ROM

1024 words x 8 ROM

1k x 8 ROM

i

word[i] = 0011word[j] = 1010

decoder

j

0

internal organization

  • 0 n-1
    • Address

bit lines (normally pulled to 1 through resistor – selectively connected to 0 by word line controlled switches)

rom read only memories1

A B C F0 F1 F2 F3

0 0 0 0 0 1 00 0 1 1 1 1 00 1 0 0 1 0 00 1 1 0 0 0 1

1 0 0 1 0 1 1

1 0 1 1 0 0 0

1 1 0 0 0 0 1

1 1 1 0 1 0 0

ROM8 words x 4 bits/word

A B C F0 F1 F2 F3

address

outputs

truth table

block diagram

ROM – Read Only Memories
  • Combinational logic implementation (two-level canonical form) using a ROM

F0 = A' B' C + A B' C' + A B' C

F1 = A' B' C + A' B C' + A B C

F2 = A' B' C' + A' B' C + A B' C'

F3 = A' B C + A B' C' + A B C'

rom structure

n address lines

• • •

inputs

memoryarray(2n wordsby m bits)

decoder

2n wordlines

outputs

• • •

m data lines

ROM structure
  • Similar to a PLA structure but with a fully decoded AND array
    • completely flexible OR array (unlike PAL)
3 larger combinational systems8
3. Larger Combinational Systems
  • 3.1 Delay in Combinational Logic Circuits
  • 3.2 Adders and Other Arithmetic Circuits
  • 3.3 Decoders
  • 3.4 Encoders and Priority Encoders
  • 3.5 Multiplexers
  • 3.6 Demultiplexers
  • 3.7 Three-State Gates
  • 3.8 Gate Arrays-ROMs, PLAs and PALs
  • 3.9 Larger Examples
3 9 larger examples
3.9 Larger Examples
  • 1. Seven-segment displays
  • 2. Comparator
comparator
Comparator
  • 1-bit full comparator:

ai > bi Gi=1

ai < bi Li=1

ai = bi Ei=1

comparator1
Comparator
  • N-bit parallel comparator:
midterm examination 90
Midterm examination (90’)
  • 1. Represent the following function in the canonical form SOP:

F(A,B,C)=(A+B’)C

  • 2. Use the Quine-McCluskey method to obtain the minimal sum for the following function:

F(A,B,C,D,E)= ∑(1,4,6,7,8,9,10,11,15)

  • 3. Design 4x16 decoder using only 2x4 decoders.
  • 4. Design a combinational logic circuit to calculate the following function: M=N+3 where N is BCD number (Binary-Coded Decimal).
midterm examination 2 90
Midterm examination 2 (90’)
  • 1. Represent the following function in the canonical form SOP and POS:

F(A,B,C)=C

  • 2. Use the Quine-McCluskey method to obtain the minimal sum for the following function:

F(A,B,C,D,E)= ∑(1,4,6,7,8,11,12,13,15)

  • 3. Using 3x8 decoder to implement the following function:

F(A,B,C) = AB + B’C

  • 4. Design a combinational logic circuit to calculate the following function: M=N+5 where N is BCD number (Binary-Coded Decimal).
slide199
Chapter 4.

Sequential Systems

4 sequential systems
4. Sequential Systems
  • 4.1 Definitions
  • 4.2 State Tables and Diagrams
  • 4.3 Latches and Flip Flops
  • 4.4 Analysis of Sequential Systems
  • 4.5 Design of Sequential Systems
  • 4.6 Solving Larger Sequential Problems
4 1 definitions
4.1 Definitions
  • Combinatorial circuit is memoryless.
  • In a circuit with memory, an output value at tn+1 must be a function not only of the inputs at tn+1 but also of the outputs at tn.
  • To achieve this, the circuit must have some feedback connections from its outputs to its inputs.

A circuit with memory is a combinatorial circuit

incorporating some feedback connections.

feedback and memory devices
Feedback and memory devices
  • To implement feedback, signals are fed back from outputs to inputs using memory devices.
  • A memory device stores an output value at time tn so that it can be input to the circuit at tn+1.
  • But then, output at tn depends on input at tn-1, which in turn depends on tn-2…

The circuit maps input sequences to output sequences

sequential circuit model
Sequential circuit model
  • Circuits with memory are called sequential circuits.

Circuit outputs

Circuit inputs

Next state

Present state

sequential circuit model1
Sequential circuit model
  • Mealy model:
      • X : finite inputs. m inputs: x1,x2...,xm
      • S : finite states. n states: s1,s2...,sn
      • Y: finite outputs. l outputs: y1,y2...,yl
      • Fs: state function. Fs = Fs(X,S)
      • Fy : output function. Fy = Fy(X,S)
  • Moore: ~Mealy
      • Difference: Fy = Fy(S)
asynchronous synchronous sequential circuits
Asynchronous/Synchronous sequential circuits
  • The timing of the signal in the circuit determine two types of sequential circuits:
    • Synchronous
    • Asynchronous.
synchronous sequential circuits
Synchronous sequential circuits
  • In a synchronous sequential circuit, the state can change only at discrete instants of time.
  • To achieve that, the circuit uses a timing device, called a clock generator, that produce trains of periodic or aperiodic clock pulses.
  • The clock pulses are input to the memory devices so that they can change state only in response to the arrival of a pulse and only once for each pulse occurrence.

The operation of the circuit is synchronized with the clock pulse input.

asynchronous sequential circuits
Asynchronous sequential circuits
  • The behavior of an asynchronous sequential circuit depends only on the order in which the inputs change and can be affected at any instant of time.
  • There is no timing device in asynchronous sequential circuit (unclocked memory).
4 sequential systems1
4. Sequential Systems
  • 4.1 Definitions
  • 4.2 State Tables and Diagrams
  • 4.3 Latches and Flip Flops
  • 4.4 Analysis of Sequential Systems
  • 4.5 Design of Sequential Systems
  • 4.6 Solving Larger Sequential Problems
state diagram
State diagram
  • Depict graphically the operation of a sequential circuit.
    • Mealy state diagram
example of state diagram
Example of state diagram
  • Example: a sequential circuit is used to detect the string “0101” from one input.
state diagram1
State diagram
  • Depict graphically the operation of a sequential circuit.
    • Moore state diagram
state table
State table
  • State table presents in a tabular form the same information contained in the state diagram.
    • Mealy state table
    • Moore state table
mealy state table
Mealy state table

PS: Present State

NS: Next State

k memory devices => 2k rows

n circuit inputs => NS portion contains 2n columns

Output portion also contains 2n columns

moore state table
Moore state table

The output portion always contains a single column.

The entry at the intersection of any row with the output column indicates the

output values corresponding to the PS associated with that row.

incompletely specified mealy state table
Incompletely specified Mealy state table
  • Two inputs: x1,x2
  • A single output: z
4 sequential systems2
4. Sequential Systems
  • 4.1 Definitions
  • 4.2 State Tables and Diagrams
  • 4.3 Latches and Flip Flops
  • 4.4 Analysis of Sequential Systems
  • 4.5 Design of Sequential Systems
  • 4.6 Solving Larger Sequential Problems
4 3 latches and flip flops
4.3. Latches and Flip-Flops
  • Simplest memory devices: Delay element

ΔT

yi

Yi

Yi

yi

yi(t+ΔT) = Yi(t)

ΔT

In practice, we don’t have to actually insert delay elements

because propagation time delays between the inputs and

the outputs of the combinatorial part of the circuit provide

sufficient delay across the feedback loops.

4 3 latches and flip flops1
4.3. Latches and Flip-Flops
  • Bistable devices:
    • Two stable states:
      • Q=0 : the device is reset (reset state)
      • Q=1: the device is set (set state)
    • A bistable device remains in one of two states indefinitely until directed by an input signal to change state.
    • Two types:
      • Latch
      • Flip-flop
4 3 latches and flip flops2
4.3. Latches and Flip-Flops
  • Latch: transparency property:
    • Change state when the input values change
    • The new output state is delayed only by the propagation time delays of the gates between inputs and outputs of the latch.
    • Used to implement the memory part of asynchronous circuits.
  • Flip-flop: no transparency property
    • Has a control (triggering) input, called clock.
    • The state change only in response to a transition of a clock pulse at clock input.
    • Used to implement memory part of synchronous circuits
sr latch

S Q

R Q’

SR Latch
  • Two inputs: S (set), R (reset)
  • Two complementary outputs: Q, Q’

Current state

Next state

Indeterminate

Q = (R+Q’)’

Q’= (S+Q)’

sr latch1

S Q

R Q’

SR Latch

Remember

Reset

Set

Equivalent characteristic table

SR=’00’ => Output no change

A logic ‘1’ at inputs can change outputs’ states

=> active-HIGH latch

sr latch2

S Q

R Q’

S Q

R Q’

SR Latch

active-HIGH SR Latch

active-LOW SR Latch

sr latch3

S

R

Q

Q

SR Latch
  • Timing chart (NOR implementation)

set

reset

set

reset

sr latch4

S

R

Q

Q

SR Latch
  • Timing chart (NAND implementation)

set

reset

set

reset

sr latch5
SR Latch

Circuit showing feedback

Excitation table

Q+ = R’Q + R’S

SR=0 => Q+ = R’Q + R’S + RS = R’Q + S

for active-HIGH SR Latch

d latch
D Latch

D

D Q

Q’

S Q

R Q’

Graphic symbol

Implementation using SR Latch

Equivalent characteristic table

Excitation table

Q* = D

gated latches

S Q

E

R Q’

Gated Latches

E: Enable input control

The latch will not change state as long as E=0

E=1 SR=10 => Set

E=1 SR=01 => Reset

  • The operation of latch is synchronized

with the E input => E: synchronous input

A latch with synchronous input is called

gated latch.

flip flops
Flip-flops
  • Latches implement memory part in asynchronous sequential circuits
  • Flip-flops do the same for synchronous circuits. FF has clock input and changes state synchronously with clock.
  • Four common types of flip-flops:
    • SR
    • D
    • JK
    • T
sr flip flop

S Q

CLK

R Q

S Q

CLK

R Q

S Q

CLK

R Q

SR flip-flop
  • The triangle called dynamic indicator, indicates that the device responds only to an input clock transition from LOW (0) to HIGH (1) => Positive edge-triggered
  • Appending a small circle to the CLK input indicates that the flip-flop responds only to an input clock transition from HIGH (1) to LOW (0) => Negative edge-triggered

Pulse-triggered

(Master-Slave)

Negative edge-triggered

Positive edge-triggered

sr flip flop1

S Q

CLK

R Q’

SR flip-flop
  • The information is entered on the leading edge of the clock pulse, but the flip-flop does change state (the output is postponed) until the trailing edge of the clock pulse.

Pulse-triggered

(Master-Slave)

Difference between Latch and Flip-flop?

  • The flip-flop can not change state except on the
  • triggering edge of clock pulse => synchronous
  • Present and next states in a latch are separated
  • In time by gate delays, they are separated by clock
  • periods in a flip-flop.
sr flip flop2
SR flip-flop

Current state

Next state

Reduced characteristic table

Excitation table

Indeterminate

Characteristic table

Q(t+1)= R’Q(t) + S

(S=1 & R=1) is inhibited

implementation of sr ff
Implementation of SR-FF

S

Q

CL

Q

R

Implementation of SR-FF by SR-Latch

S

S Q

Q

CL

SR-latch

R Q

Q

R

sr flip flop3

S Q

CLK

R Q

SR flip-flop
  • Timing chart

S

R

CL

Q

Q

d flip flop

D Q

CLK

Q’

D flip-flop
  • D flip-flop is useful for storing a single bit

D

S Q

CLK

R Q

CLK

Positive edge-triggered D flip-flop

Implementation using SR flip-flop

d flip flop1
D flip-flop

Current state

Next state

Characteristic table

Excitation table

Reduced characteristic table

Q(t+1)= D

jk flip flop

J Q

CLK

K Q’

JK flip-flop
  • JK = 00 => Q* = Q REMEMBER
  • JK = 01 => Q* = 0 RESET
  • JK = 10 => Q* = 1 SET
  • JK = 11 => Q* = not(Q) INVERT

S Q

CLK

R Q

Implementation using SR flip-flop

Positive edge-triggered JK flip-flop

jk flip flop1
JK flip-flop

Current state

Next state

Reduced characteristic table

Excitation table

Characteristic table

Q(t+1)= K’Q + JQ’

master slave flip flop
Master-Slave flip-flop
  • A pulse-triggered flip-flop is a bistable device
    • states depend on the values of synchronous inputs at the leading edge of the clock pulse
    • those states does not change until the trailling edge of the clock pulse.
master slave flip flop1

Master

Slave

S Q

E

R Q’

S Q

E

R Q’

SCR

Q

Q’

Master-Slave flip-flop
  • A pulse-triggered flip-flop consists of two latches, where one acts as a master and the other acts as a slave => Master-slave flip-flop

Master latch works when C=1

Slave latch works when C=0

edge triggered flip flop
Edge-Triggered flip-flop
  • A edge-triggered flip-flop is a bistable device whose state depends on the synchronous inputs either at the positive edge or at the negative edge of a clock pulse.
edge triggered flip flop1

Q

C

Q

D

Edge-Triggered flip-flop

Positive edge-triggered D flip-flop

Y1

Y2

edge triggered flip flop2

J

Q

CL

Q

K

Edge-Triggered flip-flop

Positive edge-triggered JK flip-flop

flip flop conversions
Flip-Flop conversions
  • Each FF can mutually converted
    • How to implement y-FF by using x-FF
    • (1) Prepare expanded state table of y-FF
    • (2) Prepare excitation table of x-FF
    • (3) Combine (1) and (2)
    • (4) Calculate logic function for each input of x-ff

combinatorial

circuit

aQ

Q

input of y-FF

x-FF

CL

b Q

Q

CL

flip flop conversions1
Flip-Flop conversions
  • Example: Implement T-FF using SR-FF

SR-FF

T-FF

Q+

0

1

1

0

T Q

0 0

0 1

1 0

1 1

S R Q Q+

0 0 0 0

0 0 1 1

0 1 0 0

0 1 1 0

1 0 0 1

1 0 1 1

1 1 0 -

1 1 1 -

Expanded state table shows the state

transition by the input

flip flop conversions2
Flip-Flop conversions
  • Example: Implement T-FF using SR-FF

expanded state table

excitation table

SR-FF

S R Q Q+

0 0 0 0

0 0 1 1

0 1 0 0

0 1 1 0

1 0 0 1

1 0 1 1

1 1 0 -

1 1 1 -

stateinput

QQ+SR

0 0 0 -

0 1 1 0

1 0 0 1

1 1 - 0

Excitation table shows the input value

corresponding to the state transition

flip flop conversions3
Flip-Flop conversions
  • Example: Implement T-FF using SR-FF

excitation table

T-FF

Q+

0

1

1

0

T Q

0 0

0 1

1 0

1 1

stateinput

QQ+T

0 0 0

0 1 1

1 0 1

1 1 0

flip flop conversions4
Flip-Flop conversions
  • Example: Implement T-FF using SR-FF

expanded state table of T-FF

Q+

0

1

1

0

T Q

0 0

0 1

1 0

1 1

T Q Q+ S R

0 0 0 0 -

0 1 1 - 0

1 0 1 1 0

1 1 0 0 1

excitation table of SR-FF

stateinput

QQ+SR

0 0 0 -

0 1 1 0

1 0 0 1

1 1 - 0

flip flop conversions5

S Q

Q

T

R Q

Q

Flip-Flop conversions
  • Example: Implement T-FF using SR-FF

Q

T Q Q+ S R

0 0 0 0 -

0 1 1 - 0

1 0 1 1 0

1 1 0 0 1

Q

0

1

T

0

1

T

0

0 -

0

- 0

1 0

0 1

1

1

Karnaugh Map of R

Karnaugh Map of S

R=TQ

S=TQ

CL

Calculate logic function for FF input

CL

flip flop conversions6
Flip-Flop conversions
  • Example: Implement D flip-flop using JK FF

Q+

0

0

1

1

D Q

0 0

0 1

1 0

1 1

D Q Q+ J K

0 0 0 0 -

0 1 0 - 1

1 0 1 1 -

1 1 1 - 0

expanded state table of D-FF

excitation table of JK-FF

stateinput

QQ+J K

0 0 0 -

0 1 1 -

1 0 - 1

1 1 - 0

flip flop conversions7
Flip-Flop conversions
  • Example: Implement D flip-flop using JK FF

Q

Q

D Q Q+ J K

0 0 0 0 -

0 1 0 - 1

1 0 1 1 -

1 1 1 - 0

0

1

D

0

1

D

0

0

0 -

- 1

- 0

1 -

1

1

Karnaugh Map of J

Karnaugh Map of K

J=D

K=D

J Q

Q

CL

CL

D

K Q

Q

4 sequential systems3
4. Sequential Systems
  • 4.1 Definitions
  • 4.2 State Tables and Diagrams
  • 4.3 Latches and Flip Flops
  • 4.4 Analysis of Sequential Systems
  • 4.5 Design of Sequential Systems
  • 4.6 Solving Larger Sequential Problems
a d flip flop moore model circuit
A D flip-flop Moore model circuit
  • D1 = q1q2’ + xq1’
  • D2 = xq1
  • z = q2’
a jk flip flop moore model circuit
A JK flip-flop Moore model circuit
  • JA = x KA = xB’
  • JB = KB = x + A’
  • z = A + B
a d flip flop mealy model circuit
A D flip-flop Mealy model circuit
  • D1 = xq1 + xq2
  • D2 = xq1’q2’
  • z = zq1
5 5 2 state reduction
5.5.2. State reduction
  • State transition diagram may include redundancy. State reduction technique aims to simplify sequential circuit by reducing redundancy of the state transition diagram.
  • Equivalence:
    • two states are equivalent if output sequences are the same when the same input sequence is given
  • Method 1: Procedure to get equivalent states
  • Method 2: Reduction of incompletely specified state table
5 5 2 state reduction1
5.5.2. State reduction
  • Examples:

A

0/0

1/0

B

C

B

C

1/1

1/1

1/1

1/1

0/0

0/0

0/0

0/0

0/0

0/0

0/0

0/0

D

E

D

E

0/0

0/0

1/0

1/0

1/0

1/0

1/0

1/0

AF

F

unify A and F

A and F have the same output and transition state for the same input

5 5 2 state reduction2
5.5.2. State reduction
  • Examples:

B

C

B

C

0/0

1/1

1/1

1/1

0/0

1/1

0/0

0/0

0/0

1/0

0/0

0/0

D

E

0/0

1/0

AF

DE

0/0

1/0

1/0

1/0

AF

unify D and E

D and E have the same output and transition state for the same input

5 5 2 state reduction3
5.5.2. State reduction
  • Examples:

BC

B

C

0/0

1/1

0/0

1/1

0/0

1/0

0/0

1/1

0/0

1/0

0/0

DE

AF

AF

DE

0/0

1/0

1/0

unify B and C

5 5 2 state reduction4
5.5.2. State reduction

next state

output

output

current

state

current

state

next state

0 1

B C

D E

E D

D F

E F

B C

0 1

B C

D E

E D

D AF

E AF

0 1

0 0

0 1

0 1

0 0

0 0

0 0

0 1

0 0

0 1

0 1

0 0

0 0

A

B

C

D

E

F

AF

B

C

D

E

current

state

next state

output

current

state

next state

output

0 1

B C

DE DE

DE DE

DE AF

0 1

BC BC

DE DE

DE AF

0 1

0 0

0 1

0 1

0 0

0 1

0 0

0 1

0 0

AF

B

C

DE

AF

BC

DE

5 5 2 state reduction5
5.5.2. State reduction
  • Method 1: Procedure to get equivalent states
    • (1) Find multiple states that have the same output with the same input, and treat them as a set of state S1 (s1,s2,…)
    • (2) Rewrite state transition table by using the set of state.
    • (3) If the next state of the member of the set are different,the set includes nonequivalent state. Then divide the nonequivalent set and iterate (2)
example of method 1 1 4
Example of method 1 (1/4)
  • Reduce the state of the state transition diagram

0/0

output

next state

0 1

a b

d c

a b

f e

d c

e a

current

state

  • 0 1
  • 0 0
  • 1
  • 0 0
  • 1 1
  • 1 1
  • 1 0

a

1/0

1/0

a

b

c

d

e

f

f

b

0/0

0/1

1/0

1/1

0/1

0/1

1/1

c

e

1/1

d

0/1

example of method 1 2 4
Example of method 1 (2/4)

output

next state

0 1

a b

d c

a b

f e

d c

e a

current

state

  • 0 1
  • 0 0
  • 1
  • 0 0
  • 1 1
  • 1 1
  • 1 0

a

b

c

d

e

f

(b,e) and d are not equivakent

hence, divide S2 into S2 and S4

(1) Find a set of state

with the same output

(2) Rewrite next state

by using set of state

a : S1,S2

c : S1,S2

S1

equivalent

a : S1,S2

c : S1,S2

S1

S1 (a,c)

S2 (b,d,e)

S3 (f)

b : S4,S1

e : S4,S1

S2

equivalent

b : S2,S1

d : S3,S2

e : S2,S1

S2

S4

d : S3,S2

S3

f : S2,S1

S3

f : S2,S1

example of method 1 3 4
Example of method 1 (3/4)

(2) Rewrite state transition table

a : S1,S2

c : S1,S2

output

current

state

S1

next state

0 1

a b

d c

a b

f e

d c

e a

  • 0 1
  • 0 0
  • 1
  • 0 0
  • 1 1
  • 1 1
  • 1 0

b : S4,S1

e : S4,S1

a

b

c

d

e

f

S2

S4

d : S3,S2

S3

f : S2,S1

output

current

state

next state

0 1

S1 S2

S4 S1

S3 S2

S2 S1

  • 0 1
  • 0 0
  • 1
  • 1 1
  • 1 0

S1

S2

S4

S3

example of method 1 4 4
Example of method 1 (4/4)

output

current

state

next state

0 1

S1 S2

S4 S1

S3 S2

S2 S1

  • 0 1
  • 0 0
  • 1
  • 1 1
  • 1 0

Generate state transition diagram

S1

S2

S4

S3

0/0

a

1/0

1/0

0/0

f

b

0/0

1

1/1

0/1

1/1

0/1

1/0

0/1

1/0

1/1

c

e

0/1

3

2

1/1

0/1

d

0/1

0/1

1/1

4

5 5 2 state reduction6
5.5.2. State reduction
  • Method 2: Reduction of incompletely specified state table
    • 1: Find non compatible pairs
    • 2: Find compatible set that doesn’t involve non compatible pairs
    • 3: Obtain maximum compatible set
    • 4: Calculate minimum closed set
    • 5: Generate reduced state transition table

Incompletely specified: don’t care appears in the next state and output

compatible pair: for every input, output are the same

example of method 2 1 5
Example of method 2 (1/5)

Implication table

current

state

next state

input X1X0

00 01 10 11

d e b -

e - - a

a - - e

- b e d

a b f -

d c - e

output

input X1X0

00 01 10 11

0 - 0 -

- 1 - 0

1 - 0 -

- 0 0 -

- - - 0

1 - 1 0

b

de

c

ae

×

a

b

c

d

e

f

d

be

×

de

ad

be

bf

e

ae

ef

f

×

de

ae

×

ad

bc

×

e

a

b

c

d

1:fill in × at incompatible pair

2: fill in conditions to be compatible

a set of not compatible pairs

(a,c) (a,f) (b,d) (c,f) (d,f)

example of method 2 2 5
Example of method 2 (2/5)

Decompose state set by non compatible pairs

(a,c) (a,f) (b,d) (c,f) (d,f)

(a,b,c,d,e,f)

(a,c)

(a,b,d,e,f)

(b,c,d,e,f)

(b,d)

(a,f)

(a,b,d,e)

(b,d,e,f)

(b,c,e,f)

(c,d,e,f)

(b,d)

(b,d)

(c,f)

(c,f)

(a,b,e)

(a,d,e)

(b,e,f)

(d,e,f)

(b,c,e)

(b,e,f)

(c,d,e)

(d,e,f)

(d,f)

remove duplicated node

remove pair involved to

other node

(d,e)

(e,f)

Maximum compatible set is (a,b,e),(a,d,e),(b,e,f),(b,c,e),(c,d,e)

example of method 2 3 5
Example of method 2 (3/5)

Logic function to represent each set involved

a: C1+C2

b: C1+C3+C4

c: C4+C5

d: C2+C5

e: C1+C2+C4+C5

f: C3

Maximum compatible set

C1:(a,b,e)

C2:(a,d,e)

C3:(b,e,f)

C4:(b,c,e)

C5:(c,d,e)

Minimum closed set is a subset of maximum compatible set that involves all the state

axbxcxdxexf = 1

(C1+C2)(C1+C3+C4)(C4+C5)(C2+C5)(C1+C2+C4+C5)C3

=(C1+C2C3+C2C4)(C2C4+C5) (C1+C2+C4+C5)C3

=(C1C5+C2C3C5+C2C4) (C1+C2+C4+C5)C3

=(C1C5+C2C3C5+C2C4)C3

=C1C3C5+C2C3C5+C2C3C4

hence (C1,C3,C5),(C2,C3,C5),(C2,C3,C4) are candidates for minimum closed set

example of method 2 4 5

Implication table

b

de

c

ae

×

d

be

×

de

ad

be

bf

e

ae

ef

f

×

de

ae

×

ad

bc

×

e

a

b

c

d

Example of method 2 (4/5)

C1:(a,b,e)

C2:(a,d,e)

C3:(b,e,f)

C4:(b,c,e)

C5:(c,d,e)

candidate for minimum closed set:

(C1,C3,C5),(C2,C3,C5),(C2,C3,C4)

check state transition of each candidate

by using Implication table

C1→(d,e)(a,d),(b,e),(b,f),(a,e) →(a,d,e)(b,e,f) →C1,C3

C2 →(b,e),(a,d),(b,e),(b,f),(e,f) →(b,e,f)(a,d) →C3,C2

C3→(a,e),(d,e),(a,d),(b,c) →(a,d,e)(b,c) →C2,C4

C4→(a,e) →(C1|C2)

C5→(d,e),(e,f) →(C2|C5),C3

C2,C3,C4 is closed

example of method 2 5 5
Example of method 2 (5/5)

C2:(a,d,e),C3:(b,e,f),C4:(b,c,e) are used

current

state

next state

input X1X0

00 01 10 11

d e b -

e - - a

a - - e

- b e d

a b f -

d c - e

output

inputX1X0

00 01 10 11

0 - 0 -

- 1 - 0

1 - 0 -

- 0 0 -

- - - 0

1 - 1 0

next state

input X1X0

00 01 10 11

C2 C3 C3 C2

C2 C4 C3 C2

C2 C4 C3 C2

output

input X1X0

00 01 10 11

0 0 0 0

1 1 1 0

1 1 0 0

current

state

a

b

c

d

e

f

C2

C3

C4

Reduced State Transition Table

5 5 3 state assignment
5.5.3. State assignment
  • State assignment is to encode the state table into binary notation, the result is a transition table that combines next-state table and the output table.
  • Better state allocation results in an easy logic function for input of FF.
  • SP (Substitution Property): indicator for good state allocation.

divide state into blocks so that the next state

of the same block exists in the same block

C

c

a

d

b

C1

C2

state is allocated to distinguish blocks

of SP

a

c

d

b

5 5 3 state assignment1
5.5.3. State assignment

next state

current

state

inputX

0

1

block 1 (q1,q2,q3)

block 2 (q4,q5,q6)

q1

q2

q3

q4

q5

q6

q2

q3

q1

q5

q6

q4

q4

q6

q5

q2

q1

q3

This partition is SP

The first bit is used to

distinguish the blocks.

next state

current state

inputX

0

1

u u u

u u u

u u u

1

2

3

1+

2+

3+

1+

3+

2+

0 0 0

0 0 1

0 1 0

1 0 0

1 0 1

1 1 0

0 0 1

0 1 0

0 0 0

1 0 1

1 1 0

1 0 0

1 0 0

1 1 0

1 0 1

0 0 1

0 0 0

0 1 0

5 6 ff excitation equation
5.6. FF excitation equation
  • FF excitation equation express each synchronous input of each flip-flop as a function of the present state and the inputs of the circuit.
  • These Boolean functions are derived directly from the combinational part of the circuit.
5 6 ff excitation equation1
5.6. FF excitation equation
  • Excitation equations:

J = xy2

K = x + y’2

D = x’y’2 + y’1y2

analysis of sequential circuits1
Analysis of sequential circuits
  • Example: analyse this sequential citcuit:
    • x: input
    • z: output
analysis of sequential circuits2
Analysis of sequential circuits
  • Excitation equations:

J = xy2

K = x + y’2

D = x’y’2 + y’1y2

y1

y2

  • Output equations:

z = xy1y’2

analysis of sequential circuits3
Analysis of sequential circuits

Output table

Circuit excittion table

analysis of sequential circuits4
Analysis of sequential circuits
  • Next-state equations:

JK Trigger:

Q(t+1)=Y1, Q = y1

Y1(t+1) = (x+y’2)’y1 + xy2y’1 = x’y1y2 + xy’1y2

D trigger:

Q(t+1)=Y2, Q=y2

Y2(t+1)=D

Y2(t+1)=x’y’2+y’1y2

analysis of sequential circuits5
Analysis of sequential circuits
  • State table

a=00

b=01

c=10

d=11

slide289
Chapter 5.

Hardware Design Languages