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This document provides an extensive overview of critical topics in digital circuits, including combinational and sequential circuits, pipelined circuits, memory types, and MIPS architecture. It covers single-cycle and two-cycle processor designs, explores advanced concepts such as hazards and caches, and examines realistic memory models. Each section breaks down essential components like adders, multipliers, flip-flops, and the intricacies of instruction fetching and execution. This resource is ideal for students and professionals seeking in-depth knowledge of digital system design.
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Updated List of Topics • M1: Combinational Circuits • M2a: Sequential Circuits • M2b: Pipelined Circuits • M3: Memories • M4: MIPS ISA • M5: Single-Cycle Processor with Magic Memory • M6a: Princeton Architecture • M6b: RAW Hazards • M7: Realistic Memory Model • M8: Caches • M9: 5-stage Processor Pipeline • M10: Exceptions • M11: Advanced Topics
M1: Combinational Circuits • adders • ripple carry adder • carry look ahead adder • multiplier • shifters • multiplexer • logic unit • ALU
M2a: Sequential Circuits • flip flops • register files • counters • multi-cycle combinational circuits • adders • multipliers • dividers
M2b: Pipelined Circuits • pipelined circuits without hazards • adders • multipliers • dividers
M3: Memories • ROM • SRAM • DRAM • Magic (Combinational) • Realistic (variable latency)
M5: Single-Cycle Processor with Magic Memory Instruction Fetch Decode Execute Writeback ALU Branch Ld/St 2-port Magic Memory
M6a: Two-Cycle Processor with Magic Memory Instruction Fetch Decode Execute Writeback ALU Branch Ld/St 2-port Magic Memory
M6a:Branch Resolution, Instruction Kill Instruction Fetch Decode Execute Writeback ALU Branch Ld/St 2-port Magic Memory
M6a: Princeton Architecture Memory Writeback Reg Write Instruction Fetch Decode Reg Read Execute Branch ALU Ld/St 1-port Magic Memory
M6a: 3-Stage Harvard Memory Writeback Reg Write Instruction Fetch Decode Reg Read Execute Branch ALU Ld/St 1-port Magic Memory
M6b: RAW Hazard Instruction Fetch Decode Execute Writeback ALU Branch Ld/St 1-port Magic Memory
M7: Realistic Memory Instruction Request Inst Resp, Decode Execute Ld/St Response Writeback ALU Branch Ld/St Req Realistic Memory
M8: Caches Instruction Request Inst Resp, Decode Execute Ld/St Response Writeback ALU Branch Ld/St Req ICache DCache Realistic Memory
