Novel BCD Adders and Their Reversible Logic Implementation for IEEE754r Format.
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Thapliyal, H. Kotiyal, S. Srinivas, M.B, “Novel BCD adders and their reversible logic implementation for IEEE 754r format,”19th International Conference on VLSI Design, 2006. Held jointly with 5th International Conference on Embedded Systems and Design, Jan, 2006.
Advisor : Dr . Shu-Chung Yi
Author : Shi-Xun Chang
Conventional BCD Adder
Proposed Carry Skip Adder
Reversible Logic Implementation of BCD Adders
Reversible Logic Implementation of Conventional BCD Adder
Reversible Logic Implementation of Carry Skip BCD Adder
IEEE 754r is the onging revision to the IEEE 754 floating point standard and a major enhancement to the standard is the addition of decimal format .
The first full adder block consisting of 4 full adders can generate the output carry “Cout” instantaneously , depending on the input signal and Cin , without waiting for the carry to be propagated in the ripple carry fashing .
The TSG gate can implement all Boolean functions.
Using TSG gates uses only 11 reversible gates and produces only 22 garbage outputs.
The three Fredkins in the middle of Figure are used to perform the AND4 operation.The single FG in the right side of Figure performs the AND-OR function.
Thanks for your attention ! for IEEE754r Format