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VLSI Testing http://www.engr.uconn.edu/~tehrani/teaching/test/index.html. Objective. Need to understand Types of tests performed at different stages Verification Testing Manufacturing Testing Acceptance testing Automatic Test Equipment (ATE) technology Influences what tests are possible

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vlsi testing http www engr uconn edu tehrani teaching test index html
VLSI Testinghttp://www.engr.uconn.edu/~tehrani/teaching/test/index.html
objective
Objective
  • Need to understand
    • Types of tests performed at different stages
      • Verification Testing
      • Manufacturing Testing
      • Acceptance testing
    • Automatic Test Equipment (ATE)technology
      • Influences what tests are possible
      • Measurement limitations
      • Impact on cost
    • Parametric test
types of testing
Types of Testing
  • Testing principle
    • Apply inputs and compare “outputs” with the “expected outputs”
  • Verification testing, or design debug
    • Verifies correctness of design and of test procedure
    • usually requires correction to design
  • Characterization testing
    • Used to characterize devices and performed through production life to improve the process
  • Manufacturing testing
    • Factory testing of all manufactured chips for parametric faults and for random defects
  • Acceptance testing (incoming inspection)
    • User (customer) tests purchased parts to ensure quality
verification testing
Verification Testing
  • Ferociously expensive
  • Often a software approach
  • But, may comprise:
    • Scanning Electron Microscope tests
    • Bright-Lite detection of defects
    • Electron beam testing
    • Artificial intelligence (expert system) methods
    • Repeated functional tests
manufacturing test
Manufacturing Test

(Also called production test)

  • Determines if manufactured chip meets specs
  • Must cover high % of modeled faults
  • Must minimize test time (to control cost)
  • No fault diagnosis
  • Tests every device on chip
  • Tests are functional or at speed of application or speed guaranteed by supplier
burn in or stress test
Burn-in or Stress Test
  • Process:
    • Subject chips to high temperature & over-voltage supply, while running production tests
  • Catches:
    • Infant mortality cases – these are damaged chips that will fail in the first 2 days of operation – causes bad devices to actually fail before chips are shipped to customers
    • Freak failures – devices having same failure mechanisms as reliable devices
sub types of tests
Sub-types of Tests
  • Parametric Tests:
    • measures electrical properties of pin electronics – delay, voltages, currents, etc. – fast and cheap.
  • Functional Tests:
    • used to cover very high % of modeled faults – test every transistor and wire in digital circuits – long and expensive.
    • the focus of this ECE 300 and today’s lecture
two different meanings of functional test
Two Different Meanings of Functional Test
  • ATE and Manufacturing World
    • any vectors applied to cover high % of faults during manufacturing test
  • Automatic Test-Pattern Generation World
    • testing with verification vectors or vectors generated without structural information, which determine whether hardware matches its specification – typically have low fault coverage (< 70 %)
t6682 ate specifications
T6682 ATE Specifications
  • Uses 0.35 mm VLSI chips in implementation
  • 1024 pin channels
  • Speed: 250, 500, or 1000 MHz
  • Timing accuracy: +/- 200 ps
  • Drive voltage: -2.5 to 6 V
  • Clock/strobe accuracy: +/- 870 ps
  • Clock settling resolution: 31.25 ps
  • Pattern multiplexing:
    • write 2 patterns in one ATE cycle
electrical parametric testing
Electrical Parametric Testing

Typical tests:

DC parametric test

  • Probe test (wafer sort) – catches gross defects
  • Contact, power, open, short tests
  • Functional & layout-related test

AC parametric test

    • Unacceptable voltage/current/delay at pin
    • Unacceptable device operation limits
economics of design for testability dft
Economics of Design for Testability (DFT)
  • Consider life-cycle cost; DFT on chip may impact the costs at board and system levels.
  • Weigh costs against benefits
      • Cost examples: reduced yield due to area overhead, yield loss due to non-functional tests
      • Benefit examples: Reduced ATE cost due to self-test, inexpensive alternatives to burn-in test, improved fault coverage
benefits and costs of dft
Benefits and Costs of DFT

Design

and test

+ / -

+ / -

+ / -

Diagnosis

and repair

-

-

Fabri-

cation

+

+

+

Manuf.

Test

-

-

-

Maintenance

test

-

Service

interruption

-

Level

Chips

Boards

System

+ Cost increase

- Cost saving

+/- Cost increase may balance cost reduction

vlsi chip yield
VLSI Chip Yield
  • A manufacturing defect is a finite chip area with electrically malfunctioning circuitry caused by errors in the fabrication process.
  • A chip with no manufacturing defect is called a good chip.
  • Fraction (or percentage) of good chips produced in a manufacturing process is called the yield. Yield is denoted by symbol Y.
  • Cost of a chip:

Cost of fabricating and testing a wafer

--------------------------------------------------------------------

Yield x Number of chip sites on the wafer

vlsi defects
VLSI Defects

Good chips

Faulty chips

Defects

Wafer

Clustered defects (VLSI)

Wafer yield = 17/22 = 0.77

Unclustered defects

Wafer yield = 12/22 = 0.55

fault modeling
Fault Modeling
  • Models are often easier to work with
  • Models are portable
  • Models can be used for simulation, thus avoiding expensive hardware/actual circuit implementation
  • Nearly all engineering systems are studied using models
  • All the above apply for logic as well as for fault modeling
why model faults
Why Model Faults?
  • I/O function tests inadequate for manufacturing (functionality versus component and interconnect testing)
  • Real defects (often mechanical) too numerous and often not analyzable
  • A fault model identifies targets for testing
  • A fault model makes analysis possible
  • Effectiveness measurable by experiments
some real defects in chips
Some Real Defects in Chips
  • Processing defects
      • Missing contact windows
      • Parasitic transistors
      • Oxide breakdown
      • . . .
  • Material defects
      • Bulk defects (cracks, crystal imperfections)
      • Surface impurities (ion migration)
      • . . .
  • Time-dependent failures (Age defects)
      • Dielectric breakdown
      • Electromigration
      • . . .
  • Packaging failures
      • Contact degradation
      • Seal leaks
      • . . .

Ref.: M. J. Howes and D. V. Morgan, Reliability and Degradation -

Semiconductor Devices and Circuits, Wiley, 1981.

defect fault and error
Defect, Fault, and Error
  • Defect (imperfection in hardware):
    • A defect in an electronic system is the unintended difference between the implemented hardware and its intended design.
  • Error:
    • A wrong output signal produced by a defective system is called an error. An error is an “effect” whose cause is some “defect”.
  • Fault (imperfection in function):
    • A representation of a “defect” at the abstracted function level is called a fault.
observed pcb defects
Observed PCB Defects

Occurrence frequency (%)

51

1

6

13

6

8

5

5

5

Defect classes

Shorts

Opens

Missing components

Wrong components

Reversed components

Bent leads

Analog specifications

Digital logic

Performance (timing)

Ref.: J. Bateson, In-Circuit Testing, Van Nostrand Reinhold, 1985.

common fault models
Common Fault Models
  • Single stuck-at faults
  • Transistor open and short faults
  • Memory faults
  • PLA faults (stuck-at, cross-point, bridging)
  • Functional faults (processors)
  • Delay faults (transition, path)
  • Analog faults
single stuck at fault
Single Stuck-at Fault
  • Three properties define a single stuck-at fault
      • Only one line is faulty
      • The faulty line is permanently set to 0 or 1
      • The fault can be at an input or output of a gate
  • Example: XOR circuit has 12 fault sites ( ) and 24 single stuck-at faults

Faulty circuit value

Good circuit value

j

c

0(1)

s-a-0

d

a

1(0)

g

h

1

z

i

0

1

e

b

1

k

f

Test vector for h s-a-0 fault

single stuck at faults contd
Single Stuck-at Faults (contd.)
  • How effective is this model?
    • Empirical evidence supports the use of this model
    • Has been found to be effective to detect other types of faults
    • Relates to yield modeling
    • Simple to use
why not multiple stuck at faults
Why Not Multiple Stuck-at Faults
  • In general, several stuck-at faults can be simultaneously present in the circuit.
  • A circuit with n lines can have 3n-1 possible stuck line combinations.
    • There are three states: s-a-1, s-a-0, and fault-free
  • Even a moderate value n will give an enormously large number of multiple stuck-at faults.
  • It’s a common practice to model only single stuck-at faults.
  • A n-line circuit can have at most 2n single stuck-at faults.
  • This number is further reduced by techniques known as Fault Collapsing.
checkpoints
Checkpoints
  • Primary inputs and fanout branches of a combinational circuit are called checkpoints.
  • Checkpoint theorem: A test set that detects all single (multiple) stuck-at faults on all checkpoints of a combinational circuit, also detects all single (multiple) stuck-at faults in that circuit.

Total fault sites = 16

Checkpoints ( ) = 10

fault simulator in a vlsi design process
Fault Simulator in a VLSI Design Process

Verification

input stimuli

Verified design

netlist

Fault simulator

Test vectors

Modeled

fault list

Test

compactor

Remove

tested faults

Delete

vectors

Low

Fault

coverage

?

Test

generator

Add vectors

Adequate

Stop

example
Example

c

a

e

d

f

b

HA

D

A

Carry

HA1

F

E

B

HA2

Sum

C

Half-Adder

Full-Adder

example30
Example

C0

S0

FA0

A0

B0

C1

S1

FA1

A1

B1

C2

S2

FA2

A2

B2

C3

S3

FA3

A3

C3

B3

fault simulation results
Fault Simulation Results

4-bit FA: 36 logic gates, 9 PIs, 5POs, 186 single stuck-at faults.

fault simulation algorithms
Fault Simulation Algorithms
  • Serial
  • Parallel
  • Deductive
  • Concurrent
  • Others
    • Differential
    • Parallel pattern
    • etc.
combinational atpg
Combinational ATPG
  • Structural vs. functional test
  • Definitions
  • Completeness
  • Conditions for finding a test
  • Algebras
  • Types of Algorithms – classical
  • Complexity
functional vs structural atpg
Functional vs. Structural ATPG

64-bit ripple-carry adder

functional vs structural contd
Functional vs. Structural (Contd.)
  • Functional ATPG – generate complete set of tests for circuit input-output combinations
    • 129 inputs, 65 outputs:
    • 2129 = 680,564,733,841,876,926,926,749,

214,863,536,422,912 patterns

    • Using 1 GHz ATE, would take 2.15 x 1022 years
  • Structural test:
    • No redundant adder hardware, 64 bit slices
    • Each with 27 faults (using fault equivalence)
    • At most 64 x 27 = 1728 faults (tests)
    • Takes 0.000001728 s on 1 GHz ATE
  • Designer gives small set of functional tests – augment with structural tests to boost coverage to 98+ %
history of algorithm speedups
History of Algorithm Speedups

Algorithm

D-ALG

PODEM

FAN

TOPS

SOCRATES

Waicukauski et al.

EST

TRAN

Recursive learning

Tafertshofer et al.

Est. speedup over D-ALG

(normalized to D-ALG time)

1

7

23

292

1574 ATPG System

2189 ATPG System

8765 ATPG System

3005 ATPG System

485

25057

Year

1966

1981

1983

1987

1988

1990

1991

1993

1995

1997

fault coverage and efficiency
Fault Coverage and Efficiency

Fault coverage =

Fault

efficiency

# of detected faults

Total # faults

# of detected faults

Total # faults -- # undetectable faults

=

atpg systems
ATPG Systems

Test

Patterns

Circuit

Description

Fault

List

Compacter

Aborted

Faults

Redundant

Faults

Undetected

Faults

Backtrack

Distribution

Test generator

With fault

simulation

sequential circuit atpg
Sequential Circuit ATPG
  • A sequential circuit has memory in addition to combinational logic.
  • Test for a fault in a sequential circuit is a sequence of vectors, which
      • Initializes the circuit to a known state
      • Activates the fault, and
      • Propagates the fault effect to a primary output
methods
Methods
  • Methods
    • Time-frame expansion methods
      • Forward time, reverse time, forward and reverse time
    • Simulation-based methods