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RISC vs. CISC. Dhiraj Parashar Shiva Prasad Behera Vivek Sharma. Overview. Introduction Key arguments Comparisons Post-RISC Current Trends. CISC Evolution. Storage and Memory High cost of memory. Need for compact code. Support for high-level languages

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risc vs cisc

RISC vs. CISC

Dhiraj Parashar

Shiva Prasad Behera

Vivek Sharma

CS654

overview
Overview
  • Introduction
  • Key arguments
  • Comparisons
  • Post-RISC
  • Current Trends

CS654

cisc evolution
CISC Evolution
  • Storage and Memory
    • High cost of memory.
    • Need for compact code.
  • Support for high-level languages
  • Ease of adding new microinstructions
  • Marketing Strategy

CS654

cisc effects
CISC Effects
  • Moved complexity from s/w to h/w
  • Compact code
  • Ease of compiler design (HLLCA)
  • Easier to debug
  • Lengthened design times
  • Increased design errors

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risc evolution
RISC Evolution
  • Increasingly cheap memory
  • Improvement in compiler technology

Patterson: “Make the common case fast”

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risc effect
RISC Effect
  • Move complexity from h/w to s/w
  • Provided a single-chip solution
  • Better use of chip area
  • Better Speed
  • Feasibility of pipelining
    • Single cycle execution stages
    • Uniform Instruction Format

CS654

key arguments
Key arguments
  • RISC argument
    • for a given technology, RISC implementation will be faster
    • current VLSI technology enables single-chip RISC
    • when technology enables single-chip CISC, RISC will be pipelined
    • when technology enables pipelined CISC, RISC will have caches
  • CISC argument
    • CISC flaws not fundamental (fixed with more transistors)
    • Moore’s Law will narrow the RISC/CISC gap (true)
    • software costs will dominate (very true)

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role of compiler risc vs cisc
Role of Compiler:RISC vs. CISC
  • CISC instruction:

MUL <addr1>, <addr2>

  • RISC instructions:

LOAD A, <addr1>

LOAD B, <addr2>

MUL A, B

STORE <addr1>

  • RISC is dependent on optimizing compilers

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comparisons
Comparisons
  • The Case for RISC (1980)
    • Introductory paper advocating RISC
  • Colwell et al. (1985)
    • Comparison studies misleading
    • Envisions use of techniques from both
  • Clark, Bhandarkar (1990)
    • MIPS M/2000 vs. VAX 8700
    • Unfair comparison (?!)

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post risc architecture
Post-RISC Architecture
  • Additional functional units for superscalar
  • Additional “non-RISC” (but fast) instructions
  • Increased pipeline depth
  • Branch prediction
  • Out of order execution

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current trends
Current Trends
  • P6 - x86 instructions decoded into RISC-like instructions (ROps)

Intel called this hack CRISC. This concept was so moronic that even Intel could not market it!

  • IA-64 - dependence on compilers for scheduling
  • Athlon – both direct execution and micro-programmed instructions

CS654

thanks

Thanks!

CS654