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332:438 Capstone Design – Computer Systems, DSD Track. Instructor: Prof. Michael L. Bushnell Teaching Assistant:Fei Xiang Course web site: http://www.caip.rutgers.edu/~bushnell ECE Department Rutgers University. Changes in ECE Undergrad. Hardware Courses. Capstone Design Course.

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332 438 capstone design computer systems dsd track

332:438Capstone Design –ComputerSystems, DSD Track

Instructor: Prof. Michael L. Bushnell

Teaching Assistant:Fei Xiang

Course web site:

http://www.caip.rutgers.edu/~bushnell

ECE Department Rutgers University

Capstone Design -- Digital Systems Lec. 1

changes in ece undergrad hardware courses
Changes in ECE Undergrad. Hardware Courses

Capstone Design -- Digital Systems Lec. 1

capstone design course
Capstone Design Course
  • Second term of a 2-term sequence
    • 1st term – Academic content (as before)
    • 2nd term – Design Project (exclusively)
    • Use automatic logic synthesis to synthesize project as Field-Programmable Gate Array
  • This course has:
    • No homework
    • No examinations
    • No Final Exam
    • Only two academic lectures

Capstone Design -- Digital Systems Lec. 1

so what are we doing here
So What Are We Doing Here?
  • A significant hardware design project:
    • Coded in Verilog
    • Mapped by the Synopsys system into a Field-Programmable Gate Array
    • Minimum Team Size: 6 people
    • Projects must adhere to a strict schedule
  • Bushnell functions as project team manager:
    • Weekly or bi-weekly design reviews – 15 minute meeting nearly every week
    • Accountability for all team members

Capstone Design -- Digital Systems Lec. 1

project deliverables

Project Deliverables

Capstone Design -- Digital Systems Lec. 1

project proposal
Project Proposal
  • Clear statement of what you will be designing
  • System block diagram
  • Statement of what system part each student will be designing
  • Estimate of # logic gates in each part
  • Due 1/30/09, or you lose ½ letter grade

Capstone Design -- Digital Systems Lec. 1

project specification and system block diagram
Project Specification and System Block Diagram
  • Statement of whether speed, cost, fault-tolerance, or low power consumption is most important (usually, some combination of the above is needed)
  • Projected clocking rate
  • Projected power consumption and power budget for each part (if power is important)
  • Fault-tolerance strategy (if important)
  • Hardware verification strategy
  • Proposed testing strategy
  • Social benefit of device being designed

Capstone Design -- Digital Systems Lec. 1

project specification and system block diagram1
Project Specification and System Block Diagram
  • Projected cost based on volume production
    • Itemized parts list:
    • Electronic chip that you are designing
    • Off-the shelf commercial chips
    • Housing
    • Power Supply
    • Battery
    • Keyboard
    • Cables
  • Due 2/6/09, or you lose ½ letter grade

Capstone Design -- Digital Systems Lec. 1

example system controller
Example System Controller

Capstone Design -- Digital Systems Lec. 1

system timing diagram
System Timing Diagram
  • Due 2/13/09, or you lose ½ letter grade

Capstone Design -- Digital Systems Lec. 1

example flow diagram
Example Flow Diagram

Capstone Design -- Digital Systems Lec. 1

mnemonic documented state diagram for controller
Mnemonic Documented StateDiagram for Controller

Capstone Design -- Digital Systems Lec. 1

slide13

Controller Timing Diagram

Capstone Design -- Digital Systems Lec. 1

detailed economic cost analysis
Detailed Economic & Cost Analysis
  • How do I do this?
    • Information sources:
      • Web search
      • Parts catalogs – chip companies, battery manufacturers, housing makers, cabling makers
      • Specifications from hardware companies for existing parts or systems that resemble yours
    • Figure out everything in the design, find its cost, and add up all of the costs
  • Due 2/13/09, or you lose ½ letter grade

Capstone Design -- Digital Systems Lec. 1

behavioral verilog code review
Behavioral Verilog Code Review
  • Everyone knows what this is
  • Complete code is not required – just a sample of your design
  • Due 2/27/09, or you lose ½ letter grade

Capstone Design -- Digital Systems Lec. 1

behavioral verilog code
Behavioral Verilog Code
  • Due 3/27/09, or you lose ½ letter grade

Capstone Design -- Digital Systems Lec. 1

behavioral verilog simulation
Behavioral Verilog Simulation
  • Same type of simulation that you did in 332:437
  • Due 3/27/09, or you lose ½ letter grade

Capstone Design -- Digital Systems Lec. 1

testing method hardware
Testing Method Hardware
  • For each module in design, you need one of these:
    • Test patterns generated by Rutgers spectral ATPG (automatic test-pattern generator)
    • Built-In Self-Testing Hardware for Random Logic using the BILBO
    • Built-In Self-Testing Hardware for Memory
  • For the entire design, you need:
    • JTAG Boundary Scan Hardware to break it into parts that can be separately tested
    • Testing plan for the interconnect between the parts
  • Due 4/10/09, or you lose ½ letter grade

Capstone Design -- Digital Systems Lec. 1

synthesized verilog logic
Synthesized Verilog Logic
  • To get this:
    • Read in behavioral design into design_vision
    • Tell it to optimize the design hardware
    • “File->Save As” command
    • Change “File format:” from .db to .v (verilog)
    • Give it a unique file name for the structural verilog code
  • Due 4/10/09, or you lose ½ letter grade

Capstone Design -- Digital Systems Lec. 1

structural verilog example
Structural Verilog Example

module adder ( addend, augend, sum, carry_in, agenerate,

propagate,

carry_in_LSB, carry_out_MSB );

input [0:2] addend;

input [0:2] augend;

output [0:2] sum;

inout [0:2] carry_in;

inout [0:2] agenerate;

inout [0:2] propagate;

input carry_in_LSB;

output carry_out_MSB;

Capstone Design -- Digital Systems Lec. 1

example continued
Example (continued)

wire n16, n17, n18, n19, n20, n21;

tri carry_in_LSB;

tri \carry_in[1] ;

tri \carry_in[2] ;

tri [0:2] agenerate;

tri [0:2] propagate;

tran( carry_in_LSB, carry_in[0]);

Capstone Design -- Digital Systems Lec. 1

example concluded
Example (concluded)

NAND2C U28 ( .A(addend[0]), .B(augend[0]), .Out(agenerate[0]) );

NAND2C U29 ( .A(addend[1]), .B(augend[1]), .Out(agenerate[1]) );

NAND2C U30 ( .A(addend[2]), .B(augend[2]), .Out(agenerate[2]) );

NAND2 U31 ( .A(n16), .B(n17), .Out(carry_in[1]) );

INV U32 ( .A(agenerate[0]), .Out(n17) );

NAND2 U33 ( .A(carry_in_LSB), .B(propagate[0]), .Out(n16) );

NAND2 U34 ( .A(n18), .B(n19), .Out(carry_in[2]) );

INV U35 ( .A(agenerate[1]), .Out(n19) );

NAND2 U36 ( .A(propagate[1]), .B(carry_in[1]), .Out(n18) );

XOR2 U37 ( .A(augend[0]), .B(addend[0]), .Out(propagate[0]) );

XOR2 U38 ( .A(augend[1]), .B(addend[1]), .Out(propagate[1]) );

XOR2 U39 ( .A(augend[2]), .B(addend[2]), .Out(propagate[2]) );

XOR2 U40 ( .A(carry_in[2]), .B(propagate[2]), .Out(sum[2]) );

XOR2 U41 ( .A(carry_in[1]), .B(propagate[1]), .Out(sum[1]) );

XOR2 U42 ( .A(propagate[0]), .B(carry_in_LSB), .Out(sum[0]) );

NAND2 U43 ( .A(n20), .B(n21), .Out(carry_out_MSB) );

INV U44 ( .A(agenerate[2]), .Out(n21) );

NAND2 U45 ( .A(carry_in[2]), .B(propagate[2]), .Out(n20) );

endmodule

Capstone Design -- Digital Systems Lec. 1

verilog logic simulation
Verilog Logic Simulation
  • Simulates the structural verilog code to see if it is correct:
    • Takes a lot longer than behavioral simulation
    • Requires you to insert module definitions in front of your code (I will supply these)
    • Ensures that automatic logic synthesis did not incorrectly generate the logic
    • Use the same testbench as for behavioral simulation
  • Due 4/10/09, or you lose ½ letter grade

Capstone Design -- Digital Systems Lec. 1

hardware fitted to a field programmable gate array chip
Hardware Fitted to a Field-Programmable Gate Array Chip
  • More about this later
  • Due 5/1/09, or you lose ½ letter grade

Capstone Design -- Digital Systems Lec. 1

testing fault coverage and test patterns
Testing Fault Coverage and Test Patterns

For combinational circuits:

For sequential circuits:

  • Due 4/24/09, or you lose ½ letter grade

Capstone Design -- Digital Systems Lec. 1

public safety and environmental impact statement
Public Safety and Environmental Impact Statement
  • Answer these conditions:
    • Is this device dangerous?
    • If so, under what conditions?
    • What precautions need to be taken with your device?
  • Does this device affect the environment?
    • Chemically, Electrically, Optically, or Otherwise?
    • How can the user avoid these problems?
  • Due 4/10/09, or you lose ½ letter grade

Capstone Design -- Digital Systems Lec. 1

final project presentation
Final Project Presentation
  • Requirements:
    • Done in Powerpoint
    • Presented to the entire class and ECE Dept. Faculty
    • Addresses each one of the deliverables (in summarized form)
    • Do not attempt to show the entire hardware – show only block diagram or 1 or 2 more interested hardware modules
  • Due 5/1/09, or you lose ½ letter grade

Capstone Design -- Digital Systems Lec. 1

final project report
Final Project Report
  • Data book description of part
  • Voluminous but clear description of everything
  • Needs to be organized with a Table of Contents
  • Needs to be grammatically correct with no spelling errors
  • Needs to be bound into a single document
  • Due 5/1/09, or you lose ½ letter grade

Capstone Design -- Digital Systems Lec. 1

confusion between verification and testing
Confusion Between Verification and Testing
  • Verification:
    • Done once in lifetime of design
    • Consists of verilog behavioral and logic simulations with testbench
    • Proves that there are no logic errors (bugs) in the design
  • Testing:
    • Done forever as long as the design is in production
    • Each chip made from the design is tested
    • Chips are quizzed by Automatic Test Equipment (grader) with test patterns (examination) and responses (student answers) are graded (checked for correctness)

Capstone Design -- Digital Systems Lec. 1