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Asynchronous Buses

Asynchronous bus. full handshake: 1. MSYN asserted2. SSYN asserted in response3. MSYN negated in response4. SSYN negated in responseAdvantages:relatively independent of timing (other than skew times)bus can take advantage of faster devices (unlike synchronous buses)Disadvantage: mor

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Asynchronous Buses

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    1. Asynchronous Buses An asynchronous bus has no master clock; instead, it uses a handshake protocol between a master and a slave device. After the master asserts the ADDRESS, MREQ and RD lines, it then asserts a special master synchronization line, MSYN and waits for a response from the slave on a slave synchronization line, SSYN. When the slave device sees MSYN, it performs the necessary operation and asserts the SSYN when it is done. 3.38

    2. Asynchronous bus full handshake: 1. MSYN asserted 2. SSYN asserted in response 3. MSYN negated in response 4. SSYN negated in response Advantages: relatively independent of timing (other than skew times) bus can take advantage of faster devices (unlike synchronous buses) Disadvantage: more complex to build eg, memory chip design and CPU design are interwoven Synchronous buses more common.

    3. Synchronous vs asynchronous Both synch and asynch involve devices reacting to signals eg. MREQ, RD, ... Synchronous: signals are enabled during a clock cycle the clock is a “master conductor” who coordinates timing of activities signals can occur during specified timing limits within cycle eg. a time duration after another signal changes eg. a time duration after clock signal rises or falls These time durations (table 3.38) are critical. If devices are too fast, they can read wrong signal. If they’re too slow, they may cause extra wait state(s) Asynchronous signals can occur at any moment after handshaking signals seen. No clock to coordinate timing cause/effect relationship via SYN line timing not as critical Synchronous devices cheaper to make devices react to signals at appropriate times during clock cycles manufacturer simply needs to ensure that time durations are respected.

    4. Bus Arbitration When more than one device wants to be the bus master, we need some bus arbitration mechanism to prevent chaos. A centralized arbitration scheme requires a dedicated bus arbiter, who determines which device is the bus master next; hence, every device connects to the bus arbiter with one (or more) bus request and one (or more) bus grant lines. priority of device = position on chain: closer devices have higher priority --> “daisy chain” can use multiple bus request and grant lines; each set represents a priority, and devices hooked up according to priority needs if multiple prioriy levels are being requested, arbiter grants bus to higher priority line each priority line is daisy chained

    5. Bus 3.39

    6. Bus

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