Performed by: Gidi Getter , Shir Borenstein Supervised by: Ina Rivkin Final Presentation

Technion - Israel institute of technology department of Electrical Engineering הטכניון - מכון טכנולוגי לישראלהפקולטה להנדסת חשמל High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות Space Wire Core for LEON3 System Performed by: Gidi Getter, Shir BorensteinSupervised by: Ina Rivkin Final Presentation 21/07/2008

Design a Space Wire core for LEON3 system. Load Leon3 system with our own IP core to GR-RASTA board. Project Definition

Space Wire is a spacecraft communication network. It is coordinated by the European Space Agency (ESA). Components are connected through low-cost, low-latency, full-duplex, point-to-point serial links. Uses data strobe encoding - differential ended signaling (DS-DE). Space Wire utilizes asynchronous communication and allows speeds between 2Mb/s and 400Mb/s. The protocol describes routing, flow control and error detection in hardware, with little need for software. What is Space Wire?

Consists of Data characters and Control characters. Data characters are 10 bits long – 1 parity bit,1 flag bit set to ‘0’ and 8 data bits. The Protocol

Control characters are 4 bits long – 1 parity bit,1 flag bit set to ‘1’ and 2 control characters. Control codes is built with the ESC character following a FCT character / Data character. The Protocol

Space Wire Usage Satellite Component A (Computer, Device, etc) Component B SW SW Router

Space Wire Link LVDS LEON3 System JTAG RS232 LEON3 Processor JTAG Dbg Link SERIAL Dbg Link AMBA AHB Bus AHBController MemoryController RAM SRAM, DRAM etc.

Space Wire Core – Top Level

ctrl_rst ctrl_rst ctrl_rst ‘1’ D Q D Q D Q gotFCT clk Space Wire Core – Controller

FCT synchronizer req clk tick ack tr_clk tick_tr Space Wire Core – Transmitter Data serialization unit – translate the character into data-strobe logic values Transmitter control unit – decides which character to transmit and manages FCT balance Early data fetch from FIFO

clk D 0 1 0 0 10 00 DCM & reset generator State controller and timer State controller and timer Space Wire Core – Receiver Time code synchronizer Serial to parallel character decoder FCT synchronizer Clock restore Initialization Null decoder

Leon3 reads data one packet at a time. All NChars are forwarded from FIFO1 to FIFO2 until EOP/EEP is detected. No further data is written into FIFO2 until is the packet was read by Leon3 and FIFO2 is empty again. Receiver FIFO

Handles all requests from processor. Reads and writes data from FIFOs to transfer between core and processor. Add bit for data/EOP. Updates Status Register. Informs available room in receive FIFO for FCT handling by transmitter. AMBA AHB Controller 9 Data clk wr_en State Machine 8 Data reset rd_en Tick_out AHB_slave_in Time_out StatusRegister AHB_slave_out Tick_in Time_in

The Space Wire core with Leon3 system was checked in logic simulation only. The Leon3 system with a custom IP core was loaded into GR-RASTA board. Coming up next: Simulation results. Logic Simulation

Logic Simulation – Transmit The processor initiate a read cycle on the bus, to the write status register address. volatile int *check_status = 0xB0000ABC; free_space = 64 - *check_status; The value of the status register is sent back to the processor.

Logic Simulation – Transmit volatile int *send_addr4 = 0xB0000000; *send_addr4 = *nchar; Data is written into transmit FIFO. 4 write cycles to transfer 4 nchars. Transmitter reads the nchars from the FIFO Transmitter sends the nchars across the link Transmitter sends the nchars across the link

Logic Simulation – Receive Receiver detectes arrival of nchar on link. The nchars are written into FIFO 1. Status register in AHB controller is updated by the number of nchars stored in FIFO2. Data is transferred from FIFO1 to FIFO2 as long as EOP was not recieved

Logic Simulation – Receive Receiver detectes arrival of EOP FIFO controller reports arrival of EOP to AHB controller. No more nchar will be tranfered to FIFO2. A character marking arrival of EOP is written to reciever FIFO1 AHB status register is updated, to report arrival of EOP to processor.

Logic Simulation – Receive The processor initiate a read cycle on the bus, to the status register address. volatile int *check_status = 0xB0100AB0; status = *check_status; The rest of the computation is done in software The value of the status register is sent back to the processor.

Logic Simulation – Receive The AHB controller reads 4 lines from receiver FIFO and collects them The processor requests to read 4 nchars The data is sent back to the processor, 4 nchars in parallel (32 bit data bus)

LEON3 design configuration. Add instantiation of the core to leon3mp.vhd (top module). Add VHDL file list of the core to Makefile. This will add the files to simulation and synthesis scripts. Write C code of the program. Compile using sparc-elf cross compiler. Create an exec file to run on board, and a memory snapshot for simulation. Simulate design using testbench provided by gaisler. Perform synthesis with synplify, using generated script. Perform P&R with ISE tool, and load bit file to board. Load exec file and run program using GRMON. Configuring LEON3 System

Add support for UART and DSU. LEON3 Design Configuration

Add instantiation of the core to leon3mp.vhd (top module). Add IP Core

Add IP Core AHB slave index number on the bus 12 MSB bits of slave address space Number of AHB slaves on the bus. Default is 8, change to 16.

Makefile Add the VHDL files of the core to “VHDLSYNFILES” parameter

Testbench Change SDRAM file to the same as SRAM file.

“make scripts” command generates tool-specific compile scripts. “make vsim” compiles all VHDL files and testbench for simulation. “make xgrlib” – GUI interface for running these commands and more. Create scripts for Simulation

Compile C code using sparc-elf cross compiler: To create an exec file to run on board: sparc-elf-gcc -O2 -g prog.c -o prog.exe To create a memory image for simulation: sparc-elf-objcopy -O srec prog.exe sram.srec Compile C Program for LEON3

Simulate design with Modelsim: run “make vsim” will compile all the files. Run synthesis: “make synplify” will create a project file (leon3mp_synplify.prj) for Synplify. These commands can be run from xgrlib GUI. Simulation and Synthesis

Can be run directly from synplify after synthesis. Constrains file to be used in ISE is provided in the LEON3 package in: “boards\gr-cpci-xc2v\leon3mp.ucf” P&R with ISE

Bit files can be programmed from PROM or Boundary Scan (JTAG). By default, the board is configured to be loaded from PROM at startup. To load a new bit file, the system must be reset. If a new bit file is loaded again before reset, the new system will not function. Problems UsingGR-CPCI-XC2V

To configure the board to be loaded only from JTAG, set jumpers to Boundary Scan Programming (Mode='101'). Problems UsingGR-CPCI-XC2V

LEON3 Debug Support Unit

LEON3 Debug Support Unit RS232 DSU connection for serial connection to PC JTAG connection for loading and debugging

GRMON is a general debug monitor for the LEON processor. Can be used to access all system registers and memory. Used for downloading and execution of LEON applications. Can access the DSU via RS232, JTAG, PCI, USB and ethernet. Can loopback UART in system and print its output on console. GRMON

Starting GRMON: With UART loopback via serial: grmon -u With UART loopback via JTAG: grmon -u -jtag GRMON command-line interface: Load a program: load <file> To run a program: run System information: info sys Displayingregister content: reg Displaying memory contents: mem <addr> GRMON

GRMON

Project main steps: Learn and implement Space Wire protocol. Integrate SW core into LEON3 system. Operate GR-CPCI-XC2V board with LEON3 system with our own IP core. Future improvements: Operate the SW core on the board with loopback, and check compatibility of protocol with SW bridge. Integrate SW core as master on AHB bus, implement interrupt and DMA for transactions. Achievements & Future Development

Performed by: Gidi Getter , Shir Borenstein Supervised by: Ina Rivkin Final Presentation