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Microprocessors 1. MCS-51 Interrupts. Interrupts. An interrupt is the occurrence of an event that causes a temporary suspension of a program while the condition is serviced by another program.

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microprocessors 1

Microprocessors 1

MCS-51 Interrupts

  • An interrupt is the occurrence of an event that causes a temporary suspension of a program while the condition is serviced by another program.
    • Allow a system to respond asynchronously to an event and deal with the event while another program is executing.
  • An interrupt driven system gives the illusion of doing many things simultaneously.
    • Of course, the CPU cannot execute more than one instruction at a time.
      • It can temporarily suspend execution of one program, execute another, then return to the first program.
    • In a way, interrupts are like subroutines. Except that one does not know when the interrupt code will be executed.
  • An embedded system is controlling a Microwave oven.
    • The main program is controlling the power element of the oven.
    • The use presses a key on the front panel to cancel the operation or change the length of cooking time.
    • The main program is interrupted. The ISR takes over, reads the keypad and changes the cooking conditions accordingly, then finishes by passing control back to the main program.
    • The main program continues according to the new conditions set by the ISR.
  • The important aspect is that the keypad entry occurs asynchronously with respect to the main program.
    • The main program cannot anticipate when the key will be pressed.
interrupts vs polling
Interrupts vs. Polling
  • Polling:
    • CPU monitors all served devices continuously, looking for a “service request flag”
    • Whenever it sees a request, it serves the device and then keeps polling
    • CPU is always “busy” with polling doing the “while any request” loop
  • Interrupts
    • If and when a device is ready and needs attention, it informs the CPU
    • CPU drops whatever it was doing and serves the device and then returns back to its original task
    • CPU is always “free”, when not serving any interrupts
interrupt service routines
Interrupt Service Routines
  • CPUs have fixed number of interrupts
    • Every interrupt has to be associated with a piece of code called “Interrupt Service Routine”, or ISR.
    • If interrupt-x is received by CPU, the ISR-x is executed
  • CPU architecture defines a specific “code address” for each ISR, which is stored in the,
    • “Interrupt vector Table (IVT)”
  • ISRs are basically “subroutines”, but they end with the RETI, instruction instead of RET
  • When an interrupt occurs, the CPU fetches its ISR code address from the IVT and executes it.
interrupt execution
Interrupt Execution
  • CPU finishes the instruction it is currently executing and stores the PC on the stack
  • CPU saves the current status of all interrupts internally
  • Fetches the ISR address for the interrupt from IVT and jumps to that address
  • Executes the ISR until it reaches the RETI instruction
  • Upon RETI, the CPU pops back the old PC from the stack and continues with whatever it was doing before the interrupt occurred
mcs 51 interrupts
MCS-51 Interrupts
  • There are 5 interrupts in the 8051.
    • Clones may differ.
    • Two external interrupts (INT0 and INT1), two timer interrupts (TF0 and TF1) and one serial port interrupt (SI).
  • Interrupts can be individually enabled or disabled. This is done in the IE (Interrupt Enable) register (A8H).
    • IE is bit addressable.
  • All interrupts correspond to bits in registers.
    • Therefore, it is possible to cause an interrupt by setting the appropriate bit in the appropriate register.
      • The end result is exactly as if the hardware interrupt occurred.
the ie register
The IE Register
  • Putting a 1 in a bit enables its interrupt.
  • Putting a 0 masks that interrupt.
interrupt priority
Interrupt Priority
  • The 8051 implements 2 types of interrupt priority.
  • User Defined Priority.
    • Using the IP register, the user can group interrupts into two levels – high and low.
      • An interrupt is assigned a “high” priority level by setting its bit in the IP register to 1. If the bit is set to 0, the interrupt gets a “low” priority.
  • Automatic Priority.
    • Within each priority level, a strict order is observed.
      • Interrupts are ordered as follows: INT0, TF0, INT1, TF1, SO.
the ip register
The IP Register
  • Putting a 1 in a bit assigns its interrupt to the high priority level.
pending interrupts
Pending Interrupts
  • If an interrupt occurs while it is disabled, or while a higher priority interrupt is active, it becomes pending.
    • As soon as the interrupt is enabled, it will cause a call.
    • It is also possible to cancel it by software by clearing the appropriate bit in the register.
response time
Response Time
  • Response time is the amount of time between the occurrence of the interrupt event and the start of execution of the service routine.
  • For the MCS-51, the shortest possible response time is 3 machine cycles and the longest is 9.
  • Interrupts are not recognized during specific instructions. An additional instruction must complete before interrupts will be recognized.
    • RETI and any instruction that modifies the contents of IE or IP.
activation levels int0 and int1
Activation Levels – INT0 and INT1
  • The activation for INT0 and INT1 can be configured to be level-triggered or edge-triggered based on bits IT0 and IT1 in the TCON register
    • For level-triggered (ITx = 0, default), a low on the pin causes an interrupt.
    • For edge-triggered (ITx = 1), a high-to-low transition causes the interrupt.
int0 and int1 contd
INT0 and INT1 (Contd.)
  • If INTx is configured as edge-triggered, then the change in value of the flag bit IEx in the TCON register is what causes the interrupt.
    • It can be forced through software.
  • If it is configured as level-triggered, then the interrupting device is what controls the value of the flag.
  • The flag will be automatically cleared at the end of the ISR.
    • After the RETI.
      • Prevents interrupts of the same type within an interrupt.
activation levels tf0 and tf1
Activation Levels – TF0 and TF1
  • The TF0 and TF1 interrupts are essentially edge-triggered.
    • The interrupt occurs when the counter goes from FFFFH to 0000H.
      • The flag goes from low to high.
  • These flags will be automatically cleared when the ISR is started.