1 / 6

ECS in RICH Upgrade

ECS in RICH Upgrade. Rui Gao, University of Oxford LHCb Electronics Upgrade Meeting 14 th April, 2012, CERN. RICH Level 0 Diagram. Level 0 Board. GBT. GBT. GBT. GBT. Level0: 1 fixed (Master) GBT with SCA 4xMaPMT (64-ch each) 8 FE IC (CLARO) per MaPMT up to 4 Add-on GBT

nodin
Download Presentation

ECS in RICH Upgrade

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. ECS in RICH Upgrade Rui Gao, University of Oxford LHCb Electronics Upgrade Meeting 14th April, 2012, CERN

  2. LHCb Electronics Upgrade, CERN, 12/04/2012 RICH Level 0 Diagram Level 0 Board GBT GBT GBT GBT • Level0: • 1 fixed (Master) GBT with SCA • 4xMaPMT(64-ch each) • 8FE IC (CLARO) per MaPMT • up to 4 Add-on GBT • Configurable DC-DC convertors • 180 SCAs in RICH1 • 240 SCAs in RICH2 FPGA GBT CLARO SCA CLARO CLARO CLARO

  3. LHCb Electronics Upgrade, CERN, 12/04/2012 ECS in RICH Upgrade • Completely redesign of Front End electronics, ECS using GBT-SCA, replacing SPECS. Functions of ECS: • Calibration & settings • MaPMT gain correction settings • Shaper threshold settings • Configuring add-on GBT modules • Monitoring • Temperature • Voltage and current • Testing • FE on-chip testing • Add-on GBT modules

  4. LHCb Electronics Upgrade, CERN, 12/04/2012 FE requirement • Future FE IC (CLARO as an example) • 8-bit register for gain and threshold settings per channel, 8 channels per chip • 16-bit global settings • Total: 80 bits per IC. • 32 FE ICs per Level 0/SCA – 2560 bits • 9 addresses per IC on a I2C bus – 4 IC / 36 address per Level 0/SCA. • Use 4 I2C masters in a SCA for FE ICs. • Add-on GBT monitoring and configure – number of bits to be followed up.

  5. LHCb Electronics Upgrade, CERN, 12/04/2012 SCA Resources • 32 I2C Masters • 4 - One per MaPMT for gain/threshold settings (via FPGA) • 4 - FE chip testing • 4 - Add-on GBT configuration and monitoring • JTAG • Reconfigure FPGA? • ADC 12bit 32-multiplexed input • 1 or more channel - temperature monitoring • 1 channel per power module - Current sensing • 1 channel per power module - Voltage monitoring • Parallel I/O • FE IC testing

  6. The End 6

More Related