1 / 39

Timers

Timers. Lecture L4.4. Reference. TIM_16B8C Block User Guide. S12TIM16B8CV1.pdf. Timers. The 9S12C32 Programmable Timer Output Compares Pulse Train Using Interrupts Input Capture Measuring the Period of a Pulse Train Using Interrupts. PIM_9DP256 Block Diagram. Timer module.

nile
Download Presentation

Timers

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript


  1. Timers Lecture L4.4

  2. Reference TIM_16B8C Block User Guide S12TIM16B8CV1.pdf

  3. Timers • The 9S12C32 Programmable Timer • Output Compares • Pulse Train Using Interrupts • Input Capture • Measuring the Period of a Pulse Train Using Interrupts

  4. PIM_9DP256 Block Diagram Timer module

  5. Timer Counter Timer Count Register (TCNT)

  6. Timer System Control Register 1

  7. Setting the timer count time Timer System Control Register 2 (TSCR2)

  8. Main Timer Interrupt Flag 2 (TFLG2)

  9. Timer Input Capture/Output Compare Select (TIOS)

  10. Timers • The 9S12DP256 Programmable Timer • Output Compares • Pulse Train Using Interrupts • Input Capture • Measuring the Period of a Pulse Train Using Interrupts

  11. Timer Input Capture/Output Compare Registers 0-7 Main Timer Interrupt Flag 1 (TFLG1)

  12. ; Delay using Output Compares TIOS EQU $0040 ; Timer Inp Cap.\Out Comp. Sel TCNT EQU $0044 ; Timer Counter Register TSCR1 EQU $0046 ; Timer System Control Reg 1 TSCR2 EQU $004D ; Timer System Control Reg 2 TFLG1 EQU $004E ; Timer Interrupt Flag Reg 1 TC6 EQU $005C ; Timer Output Compare Reg 6 OUTA EQU $FF4F ORG $4000 main jsr timer_init ldb #10 mn1 tba jsr hexasc jsr outa bsr second_delay decb bne mn1 swi

  13. timer_init ldaa #$40 staa tios ;select output compare 6 ldaa #$02 staa tscr2 ;div by 4: 2 MHz timer clock ldaa #$80 staa tscr1 ;enable timer ldd tcnt std tc6 ;tc6 = current count rts

  14. ms25_delay ;25 msec delay pshd ;save D ldd tc6 addd #50000 ;add 50000 to prev count std tc6 ldaa #$40 staa tflg1 ;clear outpt comp 6 flag msd1 ldaa tflg1 anda #$40 ;wait for timeout beq msd1 puld ;restore D rts second_delay ;delay 1 second pshb ;save B ldab #40 ;40x25ms = 1000ms sd1 bsr ms25_delay ;delay 25 ms decb ; 40 times bne sd1 pulb rts

  15. Pulse Train Example

  16. ; Pulse train using output compares 7 and 6 TIOS equ $0040 ; Timer Input Cap.;Output Comp. Select OC7M equ $0042 ; Output Compare 7 Mask Register OC7D equ $0043 ; Output Compare 7 Data Register TCNT equ $0044 ; Timer Counter Register TSCR1 equ $0046 ; Timer System Control Register 1 TCTL1 equ $0048 ; Timer Control Register 1 TSCR2 equ $004D ; Timer System Control Register 2 TFLG1 equ $004E ; Timer Interrupt Flag Register 1 TC6 equ $005C ; Timer Output Compare Register 6 TC7 equ $005E ; Timer Output Compare Register 7 ORG $800 p_width dw 6625 period dw 17500

  17. tinit ldaa #$c0 staa TIOS ; select output compares 6 & 7 ldaa #$02 staa TSCR2 ; div by 4: 2 MHz timer clock ldaa #$80 staa TSCR1 ; enable timer ldaa TCNT staa TC6 staa TC7 ; init cnt in TC6 & TC7 ldaa #$40 staa OC7M ; pulse train out PT6 clr OC7D ; PT6 goes low on TC7 match ldaa #$30 staa TCTL1 ; set PT6 high on TC6 match rts

  18. ORG $4000 pulse bsr tinit ;initialize timer pl1 ldaa #$c0 staa tflg1 ;clear output flags 6 and 7 ldd tc7 addd period std tc7 ;TC7new = TC7old + PERIOD addd p_width std tc6 ;TC6 = TC7new + P_WIDTH pl2 ldaa tflg1 ;wait for PT6 to go low on anda #$40 ; TC7 match and then high on beq pl2 ; TC6 match bra pl1

  19. Timers • The 9S12DP256 Programmable Timer • Output Compares • Pulse Train Using Interrupts • Input Capture • Measuring the Period of a Pulse Train Using Interrupts

  20. Pulse Train

  21. ; Pulse train using output compares 7 and 6 TIOS equ $0040 ; Timer Input Cap.;Output Comp. Select OC7M equ $0042 ; Output Compare 7 Mask Register OC7D equ $0043 ; Output Compare 7 Data Register TCNT equ $0044 ; Timer Counter Register TSCR1 equ $0046 ; Timer System Control Register 1 TCTL1 equ $0048 ; Timer Control Register 1 TIE equ $004C ; Timer Interrupt Enable Register 1 TSCR2 equ $004D ; Timer System Control Register 2 TFLG1 equ $004E ; Timer Interrupt Flag Register 1 TC6 equ $005C ; Timer Output Compare Register 6 TC7 equ $005E ; Timer Output Compare Register 7 TC6_IVEC equ $0FE4 ; Timer Channel 6 interrupt vector ORG $800 p_width dw 6625 period dw 17500 ORG $4000 pulsei bsr tinit ;initialize timer pl1 bra pl1

  22. tinit sei ; disable interrupts ldaa #$c0 staa TIOS ; select output compares 6 & 7 ldaa #$02 staa TSCR2 ; div by 4: 2 MHz timer clock ldaa #$80 staa TSCR1 ; enable timer ldaa TCNT staa TC6 staa TC7 ; init cnt in TC6 & TC7 ldaa #$40 staa OC7M ; pulse train out PT6 clr OC7D ; PT6 goes low on TC7 match ldaa #$30 staa TCTL1 ; set PT6 high on TC6 match ldd #tc6_intser std TC6_IVEC ; save int vector ldaa #$40 staa TIE ; enable TC6 interrupts cli ; enable interrupts rts

  23. tc6_intser ldd tc7 addd period std tc7 ;TC7new = TC7old + PERIOD addd p_width std tc6 ;TC6 = TC7new + P_WIDTH ldaa #$c0 staa tflg1 ;clear output flags 6 and 7 rti

  24. Timers • The 9S12DP256 Programmable Timer • Output Compares • Pulse Train Using Interrupts • Input Capture • Measuring the Period of a Pulse Train Using Interrupts

  25. Input Capture

  26. pwidth.asm ; Use input capture to measure width of single pulse. ; Polling mode -- no interrupts ; Use TC2 -- signal on PT2 TIOS equ $0040 ; Timer Input Cap.;Output Comp. Select TCNT equ $0044 ; Timer Counter Register TSCR1 equ $0046 ; Timer System Control Register 1 TCTL4 equ $004B ; Timer Control Register 4 TIE equ $004C ; Timer Interrupt Enable Register 1 TSCR2 equ $004D ; Timer System Control Register 2 TFLG1 equ $004E ; Timer Interrupt Flag Register 1 TC2 equ $0054 ; Timer Input Capture Register 6 org $800 pwidth dw 0

  27. pwidth.asm (cont.) org $4000 main bsr tic_init ;initialize timer bsr pulse_width ;measure single pulse width swi tic_init clr tios ; select all input captures clr tscr2 ; div by 1: 8 MHz timer clock ldaa #$80 staa tscr1 ; enable timer rts

  28. pwidth.asm (cont.) pulse_width ldaa #$10 staa tctl4 ;capture on rising edge ldaa #$04 staa tflg1 ;clear C2F flag pw1 ldaa tflg1 anda #$40 ;wait for rising edge beq pw1 ldd tc2 ;read t1 std 2,-sp ;save t1 ldaa #$04 staa tflg1 ;clear C2F flag ldaa #$20 staa tctl4 ;capture on falling edge pw2 ldaa tflg1 anda #$40 ;wait for falling edge beq pw2 ldd tc2 ;read t2 ldaa #$04 staa tflg1 ;clear C2F flag subd 2,sp+ ;d = t2 - t1 std pwidth ;save pwidth rts

  29. Timers • The 9S12DP256 Programmable Timer • Output Compares • Pulse Train Using Interrupts • Input Capture • Measuring the Period of a Pulse Train Using Interrupts

  30. ; Measuring the period of a pulse train. ; Use interrupts ; Use TC1 -- signal on PT1 TIOS equ $0040 ; Timer Input Cap.;Output Comp. Select TCNT equ $0044 ; Timer Counter Register TSCR1 equ $0046 ; Timer System Control Register 1 TCTL4 equ $004B ; Timer Control Register 4 TIE equ $004C ; Timer Interrupt Enable Register 1 TSCR2 equ $004D ; Timer System Control Register 2 TFLG1 equ $004E ; Timer Interrupt Flag Register 1 TFLG2 equ $004F ; Timer Interrupt Flag Register 2 TC1 equ $0054 ; Timer Input Capture Register 1 TC1_IVEC equ $0FEE ; Timer Channel 1 interrupt vector TOF_IVEC equ $0FE0 ; Timer overflow flag interrupt vector Out1byt equ $FF52 ; display hex value of byte at X org $800 ovcnt dw 0 ovcnt_old dw 0 tic1_old dw 0 dperiod rmb 4

  31. init_ic sei clr tios ; select input capture 1 clr tscr2 ; div by 1: 8 MHz timer clock ldaa #$80 staa tscr1 ; enable timer ldaa #$40 staa tctl4 ; rising edge of TC1 ldaa #$02 staa tflg1 ; clear any old flags ldaa #$80 staa tflg2 staa tscr2 ; enable TOI interrupt ldaa #$20 staa tie ; enable TC1 interrupt ldd #tc1_intser std TC1_IVEC ; save int vector ldd #tof_intser std TOF_IVEC ; save int vector cli rts

  32. tof_intser ldd ovcnt addd #1 std ovcnt ;inc ovcnt ldaa #$80 staa tflg2 ;clear TOF rti ovcnt TC1 ovcnt_old tic1_old

  33. tc1_intser ldd tc1 ;get new inp capture std 2,-sp ;push it ldd ovcnt ;get new ovcnt std 2,-sp ;push it ldd tic1_old ;get old inp capture std 2,-sp ;push it ldd ovcnt_old ;get old ovcnt std 2,-sp ;push it ldd 6,sp ;get new inp capture std tic1_old ;store it in tic1_old ldd 4,sp ;get new ovcnt std ovcnt_old ;store it in ovcnt_old tsx ;x = sp bsr dminus ;x -> ddiff ldd 0,x std dperiod ;store dperiod ldd 2,x std dperiod+2 ldaa #$02 staa tflg1 ;clear C1F flag rti

  34. Subtracting Double Numbers ovcnt tc1 ovcnt_old tic1_old

  35. org $4000 main bsr init_ic ;initialize timer mn0 ldx #dperiod ldab #4 mn1 jsr out1byt ;output dperiod decb ; to screen bne mn1 ldy #30 jsr ms_delay bra mn0 ; continuously

More Related