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L EAKAGE and T AMPER Resilient R andom A ccess M achine ( LTRAM )

L EAKAGE and T AMPER Resilient R andom A ccess M achine ( LTRAM ). Pratyay Mukherjee Aarhus University Joint work with Sebastian Faust, Jesper Buus Nielsen and Daniele Venturi. Provable security breaks down!. Because…. The Model. Reality. Provable security breaks down!.

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L EAKAGE and T AMPER Resilient R andom A ccess M achine ( LTRAM )

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  1. LEAKAGE and TAMPER ResilientRandomAccess Machine (LTRAM) PratyayMukherjee Aarhus University Joint work with Sebastian Faust, Jesper Buus Nielsen and Daniele Venturi

  2. Provable security breaks down! Because…. The Model Reality

  3. Provable security breaks down! Ourmainfocus More seriously ! Because…. The Model Reality Side channel attacks: Leakage/ Tampering Blakcbox

  4. Models of Tampering Tamper “whole computation” Tamper “only memory”

  5. Models of Tampering In the beginning…. Tamper “whole computation” Tamper “only memory” We are STRONGERrrr !!!

  6. Models of Tampering …..after a few years…. Tamper “whole computation” Tamper “only memory” [GLMMR 04, ……………………………..,DPW 10,…..] [IPSW 06, ….., DK 14] Existing results suffer from limitation e.g. can tamper upto 1/poly(n) A number of strong positive results e.g. split-state tampering I have better RESULTS !!!

  7. Our approach Can we protect against more Tampering with computation if we consider RAM ? Protect me ! Instead of

  8. Our Result: RAM + NMC => TRAM TCC 2014 Idea: Encode locations with NMC. Note: The computation is stored as a program. TRAM

  9. In fact we can get LTRAM Caveat: We assume tamper-proof CPU. But, the CPU is small and universal i.e. independent of the functionality. LTRAM

  10. Our LTRAM CPU Secret Disk-1 Secret Disk-2 Public disk

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