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High Rate TDC 1 Using Altera Stratix devices A proposal for a new design

High Rate TDC 1 Using Altera Stratix devices A proposal for a new design. Why this chip family? High Bandwidth differential input standard: pecl, lvds 78 channels of 840Mhz lvds input channels ( for EPS125) Close to two megabits of high speed configurable memory (ram, 2ports, fifo)

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High Rate TDC 1 Using Altera Stratix devices A proposal for a new design

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  1. High Rate TDC1Using Altera Stratix devicesA proposal for a new design Harold Sanders, Univ of Chicago, presentation 05/23

  2. Why this chip family? • High Bandwidth differential input standard: pecl, lvds • 78 channels of 840Mhz lvds input channels ( for EPS125) • Close to two megabits of high speed configurable memory (ram, 2ports, fifo) • Moderate price of approximately $510/chip • High speed logic performance—greater than 180Mhz • Achieve 1.2ns sampling window for this design • this is 1.2/sqrt12 rms error= 0.3464ns Harold Sanders, Univ of Chicago, presentation 05/23

  3. Lvds 83.33Mhz W,J=10 Harold Sanders, Univ of Chicago, presentation 05/23 ALTERA LVDS RECIEVER

  4. Original Mich drawing Harold Sanders, Univ of Chicago, presentation 05/23

  5. VME INTERFACE ALTERA EPM7128-160-7 ALTERA 1PS25 ALTERA 1PS25 Exaggerated Simplification Harold Sanders, Univ of Chicago, presentation 05/23

  6. NEW 2.304us 192 10bit words 2 port memory 32 12bit words 6.144us 512 words LVDS Equiv to 1.2ns Buffers , 10 bits wide Load synchronously@ 12ns /tick 10 bit words @12ns/tick See next slide Harold Sanders, Univ of Chicago, presentation 05/23

  7. T0000 T0002 A B C D E Gate T0000 = A*BCDEF :returns time=0000 Gate T0002= C*DEFG returns time 0011 Harold Sanders, Univ of Chicago, presentation 05/23

  8. ALGORITHM TO DETERMINE LEADING EDGE TIME • VIEW TWO SEQUENTIAL WORDs TO CATCH THE TRANSISTION BETWEEN MEMORY SLICES • FORM “AND GATES” WITH THE LEADING BIT BEING THE LAST BIT FROM THE OLD STATE FALSE: THE FOLLOWING “N” BITS TRUE. WHERE N IS THE MINIMUM TIME PERIOD OF A STATE • FOR TRAILING EDGE THE LOGIC IS THE SAME BUT THE VALUES ARE INVERTED Harold Sanders, Univ of Chicago, presentation 05/23

  9. Taken from previous design to Demonstrate technique used to extract edges Harold Sanders, Univ of Chicago, presentation 05/23

  10. 8 channels LVDS To parallel receivers Lvds input 83.33Mhz COMPILED AND FIT DEMO OF NEW DESIGN 8 channels Input buffer data to level 2 buffers Read addr generator input buffer pointer 132ns CDF clock 83.33Mhz system clock Harold Sanders, Univ of Chicago, presentation 05/23

  11. RESOURCES USED FOR DEMO COMPONENTS Harold Sanders, Univ of Chicago, presentation 05/23

  12. Physical size and power considerations • The board will operate with +5V @13A • -5V @1A • +12V@1A or less • There will be a generator for 3.3v for the COT repeater and internal use • The board will generate –5.2V for ECL receivers and • +1.8V for internal use • The board will be 9U, VME compatible to be a direct replacement for the design as supplied by Michigan Univ. • The incoming data shall be passed as trigger data to rear mounted mezzanine cards prior to entering the signal processing array of this card. Once the data enters the array, it will lose any real time information except for its encoded position. Harold Sanders, Univ of Chicago, presentation 05/23

  13. Design and delivery schedule and costs Design and simulation of prototype board Time: 9 Months 1 full time engineer + 1 graduate student Cost: 2-4 boards @$5000 /lot Assembly of two boards $1700 Material for 2+1/2 boards $6000 For a batch of 100 boards Bare boards $225/each Assembly $150/each Material $2000/each Time—6 months after go ahead Partial delivery as soon as 4 months. Harold Sanders, Univ of Chicago, presentation 05/23

  14. TESTING , CALIBRATION AND SUPPORT THIS IS A MAJOR RESPONSIBILITY THAT MUST BE SOLVED BY THE COLLABARTION, THE UNIVERSITY OF CHICAGO IS HEAVILY COMMITTED TO LEVEL1 AND SUPPORTS OTHER AREAS AND WE CAN COOPERATE IN THIS AREA WE HOPE THE SUPPORT FOR THESE TDCS WILL BE THE SAME AS PRESENT. Harold Sanders, Univ of Chicago, presentation 05/23

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