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# ENGR 2720 Chapter 10 - PowerPoint PPT Presentation

ENGR 2720 Chapter 10. State Machine Design. State Machine Definitions. State Machine: A synchronous sequential circuit consisting of a sequential logic section and a combinational logic section.

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### ENGR 2720 Chapter 10

State Machine Design

• State Machine: A synchronous sequential circuit consisting of a sequential logic section and a combinational logic section.

• The outputs and internal flip flops (FF) progress through a predictable sequence of states in response to a clock and other control inputs.

• State Variable: The variable held in the SM (FF) that determines its present state.

• A basic Finite State Machine(FSM) has a memory section that holds the present state of the machine (stored in FF) and a control section that controls the next state of the machine (by clocks, inputs, and present state).

### Mealy-Type State Machine

Mealy Machine: An FSM whose outputs are determined by both the sequential logic and combinational logic of the FSM

Classical Design Approach(Moore-Type)

• Define the actual problem.

• Draw a state diagram (bubble) to implement the problem.

• Make a state table. Define all present states and inputs in a binary sequence. Then define the next states and outputs from the state diagram.

• Use FF excitation tables to determine in what states the FF inputs must be to cause a present state to next state transition.

• Find the output values for each present state/input combination.

• Simplify Boolean logic for each FF input and output equations and design logic.

• Define the problem: Design a counter whose output progress is a 4-bit Gray code sequence. A Gray Code is a binary code that progresses such that only one bit changes between two successive codes.

2. Draw a State Diagram

3. Make a State Table

• Use Flip-flop excitation tables to determine at what state the flip-flop synchronous input must be to make the circuit go from each state to its next state.

• This is not necessary if we use “D flip-flops”,

since output Q follows input D. The D inputs are the same as next state outputs.

• For JK or T flip-flops, we would follow the same procedure as for a synchronous counters as outlined in Chapter 9

5. Simply the Boolean expression for each synchronous input

6. Draw the logic circuit for the state machine

FSM with Control Inputs(Mealy-Type)

• Same design approach used for FSM such as counters.

• Uses the control inputs and clock to control the sequencing from state to state.

• Inputs can also cause output changes not just FF outputs.

• Bubbles contain the state name and value

(State Name/Value), such as Start/0.

• Transitions between states are designated with arrows from one bubble to another.

• Each transition has an ordered Input/Output, such as in1/out1, out2.

• For example, if SM is at State = Start and if in1 = 0,

it then transitions to State = Continue and out1 = 1, out2 = 0.

• The arrow is drawn from start bubble to continue bubble.

• On the arrow the value 0/10 is given to represent the in1/out1,out2.

• There are two sates called start and continue.

• The machine begins in the start state waits for a Low in1. As long as in1 is High, the machine waits and out1 and out2 are both Low.

• When in1 goes Low, the machine makes a transition to continue in one clock pulse. Output out1 goes High.

• On the next clock pulse, the machine goes back to start. Output out2 goes High and out1 goes back Low.

• If in1 is High, the machine waits for a new Low on in1. Both outs are Low again. If in1 goes Low. The cycle repeats.

• Some modulus counters, such as MOD-10, have states that are not used in the counter sequence.

• The MOD-10 Counter would have 6 unused states (1010, 1011….1111) based on 4-bits.

• An FSM can also have unused states, such as an SM, with only 5 bubbles in the state diagram (5-states). This FSM still requires 3 bits to represent these states so there will be 3 unused states.

• These unused states can be treated as don’t cares (X) or assigned to a specific initial state.