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Multi-bunch Feedback System Review and Challenges for 1-2GHz

Multi-bunch Feedback System Review and Challenges for 1-2GHz. T. Nakamura. Japan Synchrotron Radiation Research Institute (JASRI) SPring-8. CFA Beam Dynamics Mini Workshop on Low Emittance Rings 2011, 2011-10-05. Collective Effect Study at SPring-8.

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Multi-bunch Feedback System Review and Challenges for 1-2GHz

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  1. Multi-bunch Feedback System Review and Challenges for 1-2GHz T. Nakamura Japan Synchrotron Radiation Research Institute (JASRI) SPring-8 CFA Beam Dynamics Mini Workshop on Low Emittance Rings 2011, 2011-10-05

  2. Collective Effect Study at SPring-8 • Calculation of Impedanceof Beam Pipe Components by MAFIA • Instability Simulation Based on the estimated Impedance with Home made Codes • CISR : Coupled-bunch Instability Simulation (C++) • SISR : Single-Bunch Instability Simulation • http://www.spring8.or.jp/pdf/en/ann_rep/95/p157-158.pdf • http://www.spring8.or.jp/pdf/en/ann_rep/95/p159-160.pdf • http://www.spring8.or.jp/pdf/en/ann_rep/95/p161-162.pdf • http://acc-physics.kek.jp/SAD/SAD2006/Doc/Slide/Nakamura.pdf • Observation of CSR • http://www.pasj.jp/web_publish/pasj2009pubfinal/papers/wpbta05.pdf • Resistive-Wall Impedance of ID shielded by Cu Sheet • http://accelconf.web.cern.ch/accelconf/p01/PAPERS/TPPH129.PDF • Observation of Fast Ion Instability and Cure by gap in Bunch Trains • http://accelconf.web.cern.ch/accelconf/p01/PAPERS/TPPH127.PDF • Cure of Transverse Instabilities by Chromaticity Modulation • http://accelconf.web.cern.ch/accelconf/p95/ARTICLES/WAC/WAC14.PDF • http://accelconf.web.cern.ch/AccelConf/IPAC10/papers/thobra02.pdf http://acc-web.spring8.or.jp/~nakamura

  3. Multi-bunch Feedback (Bunch-by-bunch Feedback) Feedback * Detect Oscillation by Beam Position Monitor (BPM) * Calculate the Kick to Damp its Oscillation * Drive Kicker with Power Amplifier Bunch-by-bunch Feedback (BBF) Control Oscillation Bunch-by-bunch ( independently ) Digital : ADC, DAC sampling rate = bunch rate ( fB) Required Frequency in baseband (kicker amplifier) ~ fB/2 * Suppression of Instabilities * Fast Damping of Oscillation excited by Injection perturbation * BBF Processor with FPGA based 508MS/s Processor (world first?) => SPring-8, PF, TLS, SOLEIL, SSRF, HLS, PLS (PLS-II), and several ion rings. * Simultaneous suppression of 10mA/bunch mode-coupling insta. + 0.05mA/bunch train multi-bunch Insta.

  4. Digital Bunch-by-bunch Feedback System Kicker BPM Storage Ring 180 deg. hybrid A B A-B fB: Bunch rate 500MHz -> 2GHz ~ fB/ 2 Power Amp. Front End Digital Feedback Processor Position Signal Kick Signal FPGA FIR filter ADC sampling rate fB DAC sampling rate fB Position History (Turn-by-turn) for Each Bunches Kick for Each Bunches

  5. FIR Filter (Digital Signal Processing) Position History (Turn-by-turn) FIR filter Kick

  6. FIR filter in FPGA Number of Taps FIR filter Output = Kick y0 Input = Bunch Position (turn-by-turn) x-1 x-2 x-3 Turn No -9 -8 -7 -6 -5 -4 -3 -2 -1 0 Current Turn -90 deg Phase Shift HOW?

  7. 9-tap FIR Filter for SPring-8 Storage Ring 9 Position History => Feedback Kick FIR filter coefficientsak Larger Taps Smaller Noise Power Narrower Tune Acceptance .... Number of Taps > One Period For Smaller Noise Power Phase vs. Tune Gain vs. Tune QH QV QH QV T. Nakamura, et al. http://accelconf.web.cern.ch/AccelConf/e04/PAPERS/THPLT068.pdf

  8. 2GHz system for CLIC DR 2GHz system for CLIC DR Higher frequency (Design) 2 GHz 4 x 500MHz ( SPring-8 ) Smaller beam size (Design) 2 um ( β = 5m)1/2 x 5um ( SPring-8 ) Stronger Damping (Assumption, 1/10 xτRadiation) 0.2 ms 1/2 x 0.5 ms ( SPring-8 ) Noise effect on Beam Size 4 x 2 x 2 ~ One order Higher than SP8

  9. Digital Bunch-by-bunch Feedback System Kicker BPM Storage Ring 180 deg. hybrid A B A-B fB: Bunch rate 500MHz -> 2GHz ~ fB/ 2 Power Amp. Front End Digital Feedback Processor Position Signal Kick Signal Digital Signal Process FIR filter ADC sampling rate fB DAC sampling rate fB Position History (Turn-by-turn) for Each Bunches Kick for Each Bunches

  10. Front-End RF Direct Sampling and Baseband Sampling

  11. Front-EndRF Direct Sampling and Baseband Sampling : 500MHz Baseband signal Down Conversion BPM Signal ∆ 30kHz 500MHz ± 30kHz ~ fB LPF 1/2 fB 250MHz ~ 300MHz fB± 1/2 fB 500MHz 500 ± 250MHz Direct Sampling (SPring-8) 30 kHz ~ 250 MHz Baseband Sampling 250MHz ~ 750 MHz A 0.5 fB – 1.5 fB ADC Bandwidth > 250MHz ADC Wide Bandwidth > 1.5 fRF = 750MHz ∆ 180 deg hybrid ∆ = A-B B T. Nakamura, et al., http://cern.ch/AccelConf/e08/papers/thpc128.pdf

  12. Front-EndRF Direct Sampling and Baseband Sampling : 2 GHz Baseband signal BPM Signal ∆ Down Conversion 30kHz ~2 GHz ~ fB LPF 0.5 fB 1GHz ~ 1.5 GHz fB – 1.5fB 2 GHz 2GHz ± 1GHz tens kHz ~ 1 GHz Direct Sampling Baseband Sampling 1 GHz ~ 3 GHz A ADC : ~ 1GHz ∆ 180 deg hybrid ∆ = A-B ADC : ~ 3 GHz B NS ADC12D1800RF (2.8GHz(-3dB))

  13. Front-End RF direct sampling * Less Components => Less tuning points * High Frequency requires Wide bandwidth of ADC suffers Large noise by ADC sampling jitter Baseband Sampling * More Components * Low Frequency Smaller effect of ADC sampling jitter Jitter of Mixing signal (500MHz, 2GHz) is small Square Wave Mixing * More Components * Much LOWER Frequency http://accelconf.web.cern.ch/AccelConf/e04/PAPERS/THPLT068.pdf

  14. Digital Bunch-by-bunch Feedback System Kicker BPM Storage Ring 180 deg. hybrid A B A-B fB: Bunch rate 500MHz -> 2GHz ~ fB/ 2 Power Amp. Front End Digital Feedback Processor Position Signal Kick Signal Digital Signal Process ADC sampling rate fB DAC sampling rate fB Position History (Turn-by-turn) for Each Bunches FIR filter Kick for Each Bunches

  15. Digital Feedback Processor FPGA ( Field Programmable Gate Array ) User Reconfigurable Hardware Logic Fast Parallel Low cost

  16. Digital Bunch-by-bunch Feedback System Kicker BPM Storage Ring fB: Bunch rate Harmonics = 4n A B ~500 ns A-B ADC sampling timing Digital Feedback Processor FPGA Front End fB/ 4 (<300MHz) DAC Signal Divider fB Multiplexer FIR ADC ADC FIR ADC FIR ADC FIR SPring-8 Processor (2004) tested/installed at ~ten storage rings http://accelconf.web.cern.ch/AccelConf/ica05/proceedings/pdf/P3_022.pdf

  17. Digital Bunch-by-bunch Feedback System Kicker BPM Storage Ring fB: Bunch rate Harmonics = 4n A B A-B Digital Feedback Processor FPGA Front End fB/ 4 (<300MHz) DAC fB fB Multiplexer De-Multiplexer FIR ADC FIR with Recent Fast ADC FIR FIR Dimtel

  18. Bunch-by-bunch Feedback System for 2GHz Storage Ring Kicker BPM 2GHz: Bunch rate Harmonics = 12n ( 2652 = 12x 7 x 13 x 17) A B A-B FPGA 2GS/s ADC 2GS/s DAC 167 MHz 500MHz Front End 12-bit 1, 13, FIR Multiplexer De-Multiplexer 1GS/s ADC 5, 17, FIR Power Divider 1GS/s Multiplexer FIR De- Multiplexer FIR De- Multiplexer FIR DAC FIR 2, 14, Multiplexer FIR De- Multiplexer 1GS/s ADC 6, 18, FIR De- Multiplexer FIR FIR De- Multiplexer FIR FIR AD9739A NS ADC12D1800 Xilinx Virtex-6/7

  19. Bunch-by-bunch Feedback System for 2GHz Storage Ring Kicker BPM 2GHz: Bunch rate Harmonics = 8n A B A-B FPGA 2GS/s ADC 2GS/s DAC 500MHz 250MHz Front End 12-bit 14-bit 1, 9, FIR De-Multiplexer Multiplexer 1GS/s ADC 5, 13, Power Divider FIR Multiplexer De- Multiplexer 1GS/s FIR De- Multiplexer FIR DAC 2, 10, Multiplexer FIR 1GS/s ADC De- Multiplexer FIR De- Multiplexer FIR De- Multiplexer FIR AD9739A NS ADC12D1800 Xilinx Virtex-6/7

  20. ADC resolution (How many bits ?) Step size << Beam size 2um (CLIC DR), 5um (SP8) Acceptance < Maximum Amplitude 0.2 – 0.3 mm for SPring-8 by Injection perturbation Step size = 0.25 um Acceptance = 1mm (+/- 0.5mm) for SPring-8 Number of Step = Acceptance / Step Size = 1mm / 0.25um= 4000 = 12bits => 12-14 bit ADC Maximum Amplitude Step size : 0.25um 0.2-0.3 mm Beam size : 2um ~ noise level Acceptance 1 mm (+/- 0.5mm) But Noise is much larger than step size

  21. Digital Feedback Processor for 2GHz CLIC Pre-Damping Ring bunch rate 2GHz,Harmonics 2652 = 12x 13 x 17 Required Specifications and Candidates ADC Bandwidth > 3 GHz for RF Direct Sampling > 1 GHz for Baseband Sampling NS ADC12D1800RF DAC Sampling Rate > 2 GS/s Bandwidth > 1 GHz Analog Devices AD9739A FPGA FIR filter > 167 MHz( 2GHz / 12 ) Xilinx Virtex-6/7 baseband RF direct

  22. Effect of Noise Noise => Feedback System => Kicker Excitation of Betatron motion Increase Effective Beam Size < 1/10 of Beam Sizes

  23. Noise Sources Beam Position Monitor Noise Thermal noise Amplifier Noise by AD sampling Sampling Jitter ADC, BPM signal timing jitter, … Position Resolution

  24. Residual Oscillation Excited by Noise Noise in Position Signal (BPM resolution, AD conversion, … ) x+δ Feedback Kicker Beam Residual oscillation excited by Noise SPring-8 Revolution Freq. T0 4.8 µs Total Damping Time τ~ τFB 0. 5 ms Amplitude σx< 0.1 xBeam Size 5 µm Position Resolution σδ= 10σx <mfor one passage High Position Resolution is required T. Nakamura, et al., EPAC’04, http://accelconf.web.cern.ch/AccelConf/e04/PAPERS/THPLT068.pdf T. Nakamura, NanoBeam ’05, http://atfweb.kek.jp/nanobeam/files/proceeding/proc-WG3b-12.pdf http://beam.spring8.or.jp/nakamura/papers/Nanobeam05/proc-WG3b-12.pdf

  25. Residual Oscillation Excited by Noise CLIC Damping Ring E ~ 3GeV, C ~ 400m , T0 = 1.3 µs Ver. EmittanceεV 1 pm (Norm. 5 nm) Rad. Damping Time τβ2 ms Just the assumption Feedback Damping Time τ~ τFB = 0.2 ms~ 0.1 xτβ ~ 0.1σδ Beam size (Ver.) σV2 um ( βV = 5m) Allowable Amplitude σx < 0.1 xBeam Size σV Position Resolution σδ= 2µmfor one passage

  26. ADC Performance on Noise σx~ 0.1σδ< 0.1 x Beam size : 2 um (DR) Position Resolution ADC Noise Level < σδ< 2 um (DR) Acceptance < 1 mm (+/- 0.5mm) Maximum Amplitude 0.2 – 0.3 mm for SPring-8 by Injection perturbation ADC S/N ratio > 1 mm / 2 um = 500 = 54 dB

  27. ADC S/N ratio (SNR) > 54 dB 60 dB 77 dB Baseband SNR 76 dB 75 dB 50 dB 74 dB RF direct SNR 73 dB 1 GHz 2 GHz 3 GHz 0 300MHz 0 Input Frequency Input Frequency ADC12D1800RF (12bit, 2GS/s, 0.2 ps jitter) AD 9467-250 (16bit, 250MS/s, 60fs jitter ) * The most of noise comes from Jitter of ADC clock * SNR in spec. sheets is defined for almost full swing signal For feedback, it’s Residual Signal it might be possible to keep small => lower SNR than Spec sheet

  28. ADC Noise by Sampling Jitter Residual Signal In A-B ADC Sampling Timing Jitter Noise ∆x=x2πf ∆τ x ∆τ Ext. Clock, ADC inside, … Noise can be reduced by reducing Residual Signal

  29. Residual Signal at input to ADC and Jitter of ADC Sampling => Noise

  30. BPM Difference Signal Create Difference Signal (A-B) of Two BPM Electrodes (A,B) By adjusting Signal Level and Timing 0.1dB/step = 1%/step 1% ~ 100um A 180 deg. Hybrid BPM A-B Open or Short End (100 % Reflection) BPM ADC B

  31. Residual Signal of BPM at ADC Input Reflections at Connections <= uncontrollable Shape Difference of BPM Electrodes => Bad Cancelation at 180 deg. Hybrid => Residual Signal ~ 1%/step A 180 deg. Hybrid Attenuator 6dB A-B BPM 2ns Open or Short End (100 % Reflection) BPM signal 40mm 4GHz BW Reflection 1GHz BW (bad BPM) B Attenuator 6dB

  32. Residual Signal and Jitter of ADC Sampling => Noise BPM A-B Signal to ADC Noise by Sampling Jitter ADC Sampling Timing Jitter ADC ADC Sampling Timing 2ns ∆x Noise (0.2dB = 2%) A-B ∆x= +160μm ∆τ = 0.5 ps (rms) 6dB BaseBand A A-B = 0.003 for 1 GHz = 0.009 for 3 GHz 180 deg Hybrid BPM Residual Signal = 2πf∆τ A-B B ( 0 dB ) RF direct 6dB x= 80 μm for 1GHz 80μm x=200μm for 3GHz by reflection... = 0.25 μm for 1 GHz = 1.8 μm for 3 GHz A-B σδ= x (rms) (-0.2dB = -2%) ∆x = -160μm σδ< 2m OK for 2GHz T. Nakamura, K. Kobayashi, and Z. Zhou, http://cern.ch/AccelConf/e08/papers/thpc128.pdf

  33. High Resolution Beam Position Monitor For SPring-8 0.2 nC bunch ( 100mA x 2 ns ) one passage of 2ns separation (wide band) σδ= 10σx <m

  34. High Resolution BPM by Shorted Stripline Structure V 20 mm Beam 45 mm H 1/4 part x 10 higher Resolution than Button BPM σδ= σV= 5m Almost OK for <m for Ne /bunch =1.2×109 one passage (1/3.4 of CLIC DR) T. Nakamura, http://accelconf.web.cern.ch/AccelConf/d05/PAPERS/POW027.PDF

  35. Beam Position Monitor for 2 GHz Smaller Size for Fast Response (high frequency) Lower signal level => Worse Resolution * Many BPMs for High Resolution Measurement (reduction of noise) to achieve < 2um resolution for one passage Reduction of Beam Pipe bore Resolution ~ 1/(bore)2 Sensitivity (∆V/V)/∆x ~ 1/(bore) Reduction of Noise by Residual Signal Cutoff < 3 GHz (TE modes) BPM at high beta for large beam size

  36. Kicker

  37. Kicker Transit Time Factor and Effective Length Kick to the bunch = Integral of 2L/c period Input Kicker t 2L/c Transit Time Factor L t = 0 Bunch = Reduction Factor for sin wave input Kick by sin wave input = Field Strength x Kicker Length xF Effective Length t = L/c Bunch

  38. Kicker Transit Time Factor and Effective Length L = 0.3m L = 0.15m L = 0.075m Effective Length For 1GHz ( fB = 2GHz) Many Short ( ~ 0.075m ) Kickers are required for 1 GHz (fB= 2GHz ) t at High Beta for smaller number or lower amplifier power 2L/c =2 x 0.3m/c = 1/500MHz

  39. Stripline Kickers in SPring-8 Orthogonal Kicker B Diagonal Kicker Length 40 cm -1V Length 30cm 70x40 -1 V 0 V SUS 90x40 -1 V 0 V Ey = 8V/m Ey = 8V/m Ex= 19 V/m SUS Ex = 8V/m 0V -1V 0 V 0 V 90x40 Length 7cm Length 30cm Orthogonal Kicker C Orthogonal Kicker A -1 V Ey= 12V/m 0V -1 V Ex = 16 V/m Cu 90x40 SUS 0V -1 V Ey= 18 V/m 0 V Ex = 9 V/m 0 V

  40. Power Amplifier for Kicker * Frequency : a few tens kHz – 1 GHz AR, R&K, ... * Kick Strength ~ Amplitude of beam (injection, ... ) xFeedabck Damping Time Kicker Power ~ (Kick Strength ) 2 Reduce Amplitude of beam

  41. Multi-bunch Feedback For 2GHz Bunch rate ? YES : Multi-bunch Feedback For 2GHz is Possible with Current Technologies for ADC, DAC, FPGA, BPM, Kicker, ... The development cost ~ 300 k Euro including several processors SPring-8 case in 2004, we paid Tokyo Electron Device 20 M JPY ( 150 k Euro at the rate in 2004 ) 3 Processors for 500MHz, FPGA program, Linux device driver / Application for USB control Half year after specification was fixed Acknowledgement: K. Kobayashi (SPring-8) for development of SPring-8 feedback Tokyo Electron Device Limited (http://www.teldevice.co.jp/eng/index.html) for the help at the development of SPring-8 feedback and discussion on performance of current FPGA

  42. If Lower Noise More Number of Bits are Required How about Square Wave Mixing Front-End

  43. Lower Noise, More Bits => Square Wave Mixing Front-End AD 9467-250 (16bit, 250MS/s) If Lower Noise More Number of Bits 75 dB SNR are Required 73 dB SNR 16-bit ADC ( AD 9467-250 ) Slow Sampling Rate < 250 MHz Low Input Frequency < 300MHz for S/N ratio > 70dB 0MHz 300MHz Square Wave Mixing (24-way) Sampling Rate : 2 GS/s => 167 MS/s Bandwidth : 1 GHz => 150 MHz Big margin for Sampling Jitter! Low jitter Frequency divider fB=> fB/12 is required (or Frequency Multiplier fB/12 => fB )

  44. Square Wave Mixing : 6-way (500MHz/2 -> 117 MHz) Low Jitter !! 85 MHz =500/6. ADC 6ns 500MHz, 6-way 250 MHz => 117MHz 85 MS/s 117MHz ADC 2ns Signal Divider ADC 2GHz , 24-way 1GHz => ~ 117MHz, 167MS/s ADC 1ns ADC ADC Contamination from Neighboring bunches Frequency Response by contamination ADC sampling T. Nakamura, et al. http://accelconf.web.cern.ch/AccelConf/e04/PAPERS/THPLT068.pdf

  45. Simultaneous suppression of 10mA/bunch mode-coupling instability + 0.05mA/bunch train multi-bunch Instability By Bunch Current Sensitive Automatic Attenuator EPAC’08, Genoa ICALEPCS’09, Kobe

  46. Digital Bunch-by-bunch Feedback System Storage Ring High Efficiency Kicker High Resolution BPM Bunch train Singlet 10 mA 0.05mA/bunch A B A-B A+B Kick Signal Bunch Current x Position Position ADC 1/Bunch Current Bunch Current ADC ( Fast Variable Attenuator ) FPGA 12-bit ADC Signal Divider FPGA Signal Divider Digital Control ADC 12-bit ADC Digital Signal Processing ( FIR filter ) Bunch Current => Attenuation Analog Control ADC DAC 12-bit ADC DAC 508MS/s 12-bit ADC Bunch Current Sensitive Automatic Attenuator SPring-8 Feedback Processor

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