Low Power Design of Integrated Systems. Assoc. Prof. Dimitrios Soudris firstname.lastname@example.org. Technology Directions: SIA Roadmap. Technology Process Evolution. Technology Directions: SIA Roadmap 2002. Transistors. #Transistors. Frequency. Performance. Performance. Power Consumption.
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Low Power Design of Integrated Systems Assoc. Prof. Dimitrios Soudris email@example.com
Technology Process Evolution Technology Directions:SIA Roadmap 2002
Power Consumption Power consumption
Power Terminology • Power is the rate at which energy is delivered or exchanged » electrical energy is converted to heat energy during operation • Power Dissipation - rate at which energy is taken from the source (Vdd ) and converted into heat
Why Smaller Power? • Large Market of Portable devices • e.g. laptops, mobile phones • Achieve larger transistor integration • Pentium IV contains 42 million transistors • Teraflops chip contains 1.9 billion transistors • Need for “green” computers • 10% of total electrical energy consumed by PCs
The Industry’s Reaction • Reduce chip capacitance through process scaling ==> Expensive • Reduce Voltage levels from 5V ί 3.3V ί 2V ==> Industry is hard to move (microprocessors, memory,...) • Better Circuit Techniques ==> Gated clocks, Power-Down of non-operational units… • Example: IBM 80 MHz PowerPC RISC (3 W @ 3.3V) • Power Management Logic determines activity on per cycle basis • Clocks of idle blocks are turned off ί 12-30% savings • Doze - Nap and Sleep mode (5 mW)
Example: Intel Pentium-II processor • Pentium-1: 15 Watt (5V - 66MHz) • Pentium-2: 8 Watt (3.3V- 133 MHz)
Where Does Power Go in CMOS? • • The power consumption in digital CMOS circuits • Pavg = Pdynamic + Pshort-circuit + Pleakage • Dynamic Power Consumption Charging and Discharging Capacitors • Short Circuit Currents Short Circuit Path between Supply Rails during Switching • Leakage (Static) Leaking diodes and transistors
Dynamic Power Consumption(1) • where VDD supply voltage, CL capacitance, N is the average number of transitions per clock cycle, and f frequency operation
Dynamic Power Consumption (2) • For technologies up to 0.35 m, the dynamic consumption is about 80% of the total consumption • Goal ===> reduce dynamic power consumption • reduction capacitance • reduction of supply voltage • reduction of frequency • reduction of switching activity • or combination of above factors
Leakage current consumption • the reverse-bias diode leakage at the transistor drains and • the sub-threshold current through an turned-off transistor channel
Power consumption of transfer and storage over datapath operations both in hardware [Men95] and software [Tiw94, Gon96] .
Architecture Power Optimization Techniques • Architecture-driven voltage reduction: The key idea is to speed up the circuit in order to be able reduces voltage while meeting throughput rate constraints. Voltage reduction can be achieved by introducing parallelism in hardware or inserting flip-flops • Switching activity minimization: Try to prevent the generation and propagation of spurious transitions or to reduce the number of transitions, e.g. retiming, path balancing, data representation • Switched capacitance minimization: Aim at the minimization of switched capacitance • Dynamic power management: Under certain conditions, a circuit part becomes inactive, avoiding unnecessary calculations, e.g. gated clocks, operand isolation, pre-computation, and guarded evaluation
Architecture Trade-offs: Reference Data Path • Critical path delay Tadder + Tcomparator (= 25ns), fref = 40MHz • Total capacitance being switched = Cref • Vdd = Vref= 5V • Power for reference datapath = Pref = CrefVref2 fref
Voltage Reduction Technique: Parallelism • The clock rate can be reduced by half with the same throughput fpar = fref / 2 • Vpar = Vref / 1.7 Cpar = 2.15 Cref • Ppar = (2.15 Cref ) (Vref /1.7)2 (fref /2) 0.36 P ref
Voltage Reduction Technique: Pipeline • fpipe = fref, Cpipe = 1.1 Cref, Vpipe = Vref /1.7 • Voltage can be dropped while maintaining the original throughput • Ppipe = CpipeVpipe2fpipe = (1.1 Cref ) (Vref /1.7)2fref = 0.37 Pref
Logic Style and Power Consumption • Power-delay product improves as voltage decreases • The “best” logic style minimizes power-delay for a given delay constraint
Data representation • Sign-extension activity significantly reduced using sign-magnitude representation
Signals and Operations Reordering • Example: complex multiplication Trading a multiplication for an addition
Two-Level Logic Circuits Switching Activity Minimization (1) • Taking into account the static and transition probabilities (i.e. temporal correlation) of the primary inputs, we can insert in certain gates of the first logic level (i.e. AND gates), additional input signals resulting into reduced switching activity • Appropriately-selected input signals force the outputs of the AND gates to logic level zero for a number of combinations of the binary input signals
Two-Level Logic Circuits Switching Activity Minimization (2) • Example: • Signal x3 exhibits low-transition probability and high static-1 probability, while the signals x0 , x1, and x2 are characterized by high-transition probabilities
Additional Info • A. Chandrakasan and R. Brodersen, “Low Power CMOS Design”, Kluwer Academic Publishers, 1995 • Christian Piguet, Editor, « Low-Power Electronics Design”, CRC Press, November 2004 • D. Soudris, C. Piguet, C. Goutis, “Designing CMOS Circuits for Low-Power”, Kluwer Academic Press, October 2002 • F. Catthoor, K. Danckaert, et. al.: 2002, Data Access and Storage Management for Embedded Programmable Processors. Kluwer Academic Publishers • Stamatis Vassiliadis and Dimitrios Soudris, “Fine- and Coarse-Grain Reconfigurable Computing” Springer, Dordrecht/London/Boston, August 2007 • http://vlsi.ee.duth.gr/~dsoudris • AMDREL website http://vlsi.ee.duh.gr/amdrel