Recent results from R&D towards a vertex detector at the international linear collider - PowerPoint PPT Presentation

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Recent results from R&D towards a vertex detector at the international linear collider

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Recent results from R&D towards a vertex detector at the international linear collider
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Recent results from R&D towards a vertex detector at the international linear collider

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  1. 2nd ECFA workshop on Physics and Detectors at the Linear Collider Durham, 1st September 2004 Recent results from R&D towards a vertex detector at the international linear collider • Introduction • Physics studies • Thin ladder development • Column parallel CCD and readout chip • ISIS based detector • Future plans Sonja Hillert, University of Oxford, on behalf of the LCFI collaboration

  2. A vertex detector for the future LC • Precision measurements require: • good angular coverage (cos q = 0.96) • proximity to IP, large lever arm: • 5 layers, radii from 15 mm to 60 mm • minimal layer thickness ( < 0.1% X0 ) • to minimise multiple scattering • mechanically stable, low mass support • low power consumption • High hit density near interaction point requires: • small pixel size: 20 mm  20 mm • fast readout: • NLC / GLC: 8ms, use Column-Parallel CCDs (CPCCDs); read between bunch trains • TESLA: 50ms for CPCCDs or 125ms for ISIS-based detector

  3. Physics Studies • aim: investigate benchmark processes to quantify tradeoffs between • requirements on detector precision and integrated luminosity • improvement of tools for these studies: • track attachment to secondary vertex • flavour tagging • examples: • study of impact parameter resolution in Rf at track perigee(right): increasing • material budget has moderate effect, • but performance strongly suffers when beam • pipe radius is increased from 15 to 25 mm • study of vertex charge reconstruction see talk in detector performance session

  4. Thin-ladder development profile of silicon along the length of a ladder How can ladders be made as thin and mechanically stable as possible? • currently focussing onsemi-supported silicon, thinned to epitaxial layer (> 20 mm): • silicon glued to substrate, e.g. beryllium, carbon fibrecomposites, ceramics, foams; • difference in expansion coefficient between Si and substrate can give rise to buckling when lowering the temperature • studied both by FEA and by measurements • on physical models (left); • plot: comparison of steel (similar to Be) and carbon fibre (CF) substrate at room temperature and ~ - 50oC: • strong buckling of the steel substrate (blue), • carbon fibre stable at low temperature (red); but: CF less favourable than Be in terms of the material budget  under further investigation • future option: Novel Structures: replace glue pillars; micromechanical engineering

  5. Column parallel CCD and readout chip • core of LCFI R&D: development of sensors • and their dedicated readout chip (CPR) • first CCD (CPC1) received April 2003, • CPR1 in June 2003 • excellent standalone performance of both devices • clock amplitudes down to 2 Vpp and clock frequencies up to 25 MHz reached • first assembly of CPC1-CPR1 (start January 2004): • in part of CCD every 3rd channel connected using wire bonds • proof of principle of reading CPC with CPR • combined test of different types of channels on both devices • connections at 20mm pitch only possible using solder bump bonds • since LCWS (April): detailed tests of first bump-bonded assembly (ongoing)

  6. The first CCD prototype (CPC1) Direct connections and 2-stage source followers • two phase, pixel size 20 μm  20 μm • 400 (V)  750 (H) pixels • two charge transport regions • wire and bump bond connection pads to readout chip and external electronics 1-stage source followers and direct connections on 20 μm pitch

  7. Readout Chip CPR1 6 mm Wire/bump bond pads • ASIC for CPC-1 readout • design: RAL Microelectronics Group • voltage amplifiers for 1-stage SF outputs • charge amplifiers for direct outputs • 20 μm pitch, 0.25 μm CMOS process • wire- and bump-bondable • scalable and designed to work at 50 MHz Charge Amplifiers Voltage Amplifiers Voltage Amplifiers Charge Amplifiers 250 5-bit flash ADCs 250 5-bit flash ADCs 6.5 mm 250(W)132(L)5-bit FIFO 250(W)132(L)5-bit FIFO Wire/bump bond pads

  8. Wire-bonded CPC1-CPR1 assembly spectrum: X-ray signals generated in CPC1 (1-stage source followers), amplified and digitised in CPR1 (voltage amplifier channels) total noise ~130 electrons, noise from preamplifiers negligible

  9. Bump-bonded CPC1-CPR1 assembly • bump bonding performed • by VTT (Finland) • connecting to CCD channels at • effective pitch of 20mm possible • by staggering of solder bumps

  10. Initial tests of bump-bonded assembly • 7 assemblies delivered by VTT, first 3 tested: • ADCs tested by applying test voltage; • CPC1-CPR1 with X-rays from 55Fe source: • 3 chips work fine ( next page), • 3 failed because of dicing problems – will be avoided in the future • working CPR1 chips: • all ADC channels functional • all charge amplifiers functional • 20% voltage amplifiers on working CPR1 chips show no signal, under further investigation • next batch of assemblies in production at VTT

  11. Results from bump-bonded assembly Voltage channels (below): gain at centre is ½ the gain at the edge: timing problem? signal in charge channels (above): 86 mV expected, 70 mV observed  very good agreement

  12. ISIS-based detector • TESLA: signals of 1000 e- to be amplified & read; • so far envisaged 20 readouts / bunch train • SLC experience: • may be impossible due to beam–related RF pickup • started to investigate alternative architecture: • variant of Image Sensor with In-situ Storage (ISIS) • Idea: • charge collection on photogate • in each pixel: linear CCD with 20 elements, each storing charge collected during 1 time slice, • shifted on at 50 ms intervals • during 200 ms between bunch trains: transfer of stored signals to local charge sensing circuits in pixel, column-parallelreadout at moderate rate, e.g. 1MHz

  13. Future plans • ongoing detailed tests of bump bonded assembly of CPC1-CPR1; • dedicated CPR1 test board for further study of various CPR1 related issues • design of next generation of CCD and CPR near conclusion • CPC2 to comprise following features: • 3 different sizes, including ‘full length’ devices to be tested at frequencies of few MHz • high-speed ‘busline-free’ devices (differing from standard devices in metallisation) • ISIS test structure for proof of principle: 16x16 cells on an x-y-pitch of 160 mm x 40 mm • CPR2 characteristics to include: • on-chip cluster finding, allowing sparsified readout • Future evaluation will show, which of our two baseline detector designs for the • cold machine option – CPCCDs or ISIS – will be better matched to the requirements. • ISIS R&D still in very early stage ~ much room for further ideas • broader international collaboration would be welcome