main objective n.
Download
Skip this Video
Loading SlideShow in 5 Seconds..
Main Objective: PowerPoint Presentation
Download Presentation
Main Objective:

Loading in 2 Seconds...

play fullscreen
1 / 9

Main Objective: - PowerPoint PPT Presentation


  • 140 Views
  • Uploaded on

Main Objective:. A comparison between single-edge-triggered Flip-Flop(SET FF) and double edge triggered Flip-Flop based Bit-serial adder in terms of power and speed. Project states:. Literature and investigations. Choosing a suitable DETFF. Bit serial adder circuit construction.

loader
I am the owner, or an agent authorized to act on behalf of the owner, of the copyrighted work described.
capcha
Download Presentation

PowerPoint Slideshow about 'Main Objective:' - morna


An Image/Link below is provided (as is) to download presentation

Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author.While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server.


- - - - - - - - - - - - - - - - - - - - - - - - - - E N D - - - - - - - - - - - - - - - - - - - - - - - - - -
Presentation Transcript
main objective
Main Objective:
  • A comparison between single-edge-triggered Flip-Flop(SET FF) and double edge triggered Flip-Flop based Bit-serial adder in terms of power and speed.
project states
Project states:
  • Literature and investigations.
  • Choosing a suitable DETFF.
  • Bit serial adder circuit construction.
  • Power preliminary comparisons.
  • Comments & next steps.
choosing a det ff

clk

PLO

M4

M13

M1

clk

Q

NLO

D

In

M5

M14

M2

Q

clk

M6

M3

clk

clk

clk

F

clk

M10

M7

Static DET FF

PLO

M15

M11

M8

In

NLO

M16

M12

M9

X

Q

clk

clk

D

A

clk

clk

Choosing a DET FF

outb

clk

SN/SP-BAL-CS Dynamic DET FF

conventional not fully pipelined bit serial adder 1

1D

C1

1D

C1

Cn

S7

S6

S5

S3

S2

S0

S4

S1

1D

C1

C7

C2

C6

C5

C4

C3

C1

C0

b7

b6

b2

b0

b5

b4

b3

b1

b

S

+

a7

a5

a2

a6

a4

a3

a1

a0

1D

C1

a

Cn+1

Cn+1

Conventional not-fully-pipelined bit-serial adder [1]
  • A sum output every clock cycle [1].
  • Single edge triggered based activity.
dual edge triggered ff based bit serial adder 2
Dual edge triggered FF-based bit-serial adder [2]
  • Output every half clock cycle under a 50% duty cycle restriction.
  • 4 Mux’s were added

F

1D

C1

a3,a2,a1,a0

0

1

1D

C1

1

0

S3,S2,S1,S0

ADD

o

1D

C1

1D

C1

o

S

1D

C1

1D

C1

1

0

0

1

b3,b2,b1,b0

o

cy1

1D

C1

1D

C1

o

[2]

preliminary power comparison results
Preliminary power comparison results
  • Aggressive sizing is needed to push the speed of the FF and the circuit.
  • Moving forward with the frequency is bounded by the adder circuit and the correct functionality of the DETFF. (I might need to switch to dynamic DETFF.)
  • Low power will be the first priority.
  • A repetitive architecture (parallelism=> f/4) could be a good approach to lower VDD while maintaining the same throughput.

194 uw

92 uw

116 uw

slide7

0 1

a3,a2,a1,a0

F

1D

C1

1D

C1

1D

C1

1D

C1

S

cy

ADD

S3,S2,S1,S0

F

F

S2,S0

S3,S1

ADD

1D

C1

1D

C1

o

S

cy

1D

C1

cy1

F

o

cy1

b3,b2,b1,b0

o

1D

C1

o

references
References

[1] J. Yuan and C. Svensson, “High-Speed CMOS Circuit Technique,”

IEEE J. Solid-State Circuits, vol. 24, no.1, pp.62-70, Feb. 1989.

[2] J. Yuan and C. Svensson, “New Single-Clock CMOS Latches and

Flipflops with Improved Speed and Power Savings,” IEEE

J. Solid-State Circuits, vol. 32, no.1, pp.62-69, Jan. 1997.

[3] W. M. Chung and M. Sachdev, “A Comparative Analysis of Dual Edge

Triggered Flip-Flops,”

[4] R.P. Llopis and M. Sachdev, “Low Power, Testable Dual Edge

Triggered FlipFlops”, International on Low Power Electronics and

Design, 1996, pp.341-5.

[5] A.G.M. Strollo, E. Napoli, and C. Cimino, “Analysis of Power

Dissipation in Double Edge-Triggered Flip-Flops,” IEE Trans. On

VLSI Systems, Vol. 8, no.5, Oct. 2000.

references1
References
  • [6] S.M.M. Mishra, S.S.Rofail and K.S.Yeo, “Design of High Performance
  • [7] Double Edge-Triggered Flip-Flops,” IEEE Proc. Circuits Devices Syst., Vol.147, no.5, Oct. 2000.
  • [8] Dual edge clocking schemes and alternate edge clocking J.Knight.