CPU Intro

1. CPU Intro CS/COE 0447 Jarrett Billingsley

2. Class announcements • OMETs are up!!! • ≥70% completion == homemade cookies for the final • so do them! CS447

3. Parts of the CPU CS447

4. We have all the pieces now… • we've learned about how hardware can… + do any kind of boolean logic… A make decisions… Y D D Q Q outputs do math… B en inputs LET'S MAKE A CPU!!! outputlogic S and do multi-step procedures. remember things… transitionlogic stateregister CS447

5. Remember this? • unresolved questions: • what's the control? • what's the datapath? • how does it know what instruction to get next? • how does it know which registers to access? • how does it know whether it should add, subtract, etc.? Memory Program Control Registers 3 5 8 instruction B A C Datapath + Processor CS447

6. Zooming in • there are a few major parts of any CPU: hi i'm memory!! Control the control tells everything else what to do, and when if(add) do this else if... ÷ Datapath Registers fp + × t0 - s4 ⊕ at ☃ control signals! ∫ & sp eax? values move between them registers hold the values being computed the datapath computes new values CS447

7. OKAY, MEMORY, WHAT DO YOU WANT?? • registers are just a temporary stopping point for your program's data • you could have a computer with few/no registers at all! Memory Control this is a memory-memorymachine Datapath if you squint and wave your hands really hard, every computer is. the registers and the memory only differ in their speed and size. CS447

8. ISA and hardware design CS447

9. Remember what an ISA is? • it's the software interface the programmer uses to control the CPU • what are some important aspects of the MIPS ISA? what instructions does it have? how many registers does it have? how are they encoded into binary? how big are they? are there any special registers? how many operands do they have? how does it access memory? the ISA abstracts the hardware design (the microarchitecture) but the microarchitecture must implement the ISA, so… CS447

10. Only kindasorta MIPS • we'll use MIPS for context… • but this stuff applies to virtually any architecture. • such as the architecture you'll implement for the project!! • the book doesn't use MIPS either • it uses DLX: a simplified, modernized version of MIPS • the hardware in the book is extremely hand-wave-y (what's jal?) • but they go into way more detail than needed for some things… CS447

11. The register file • the register file is what holds the GPRs – general-purpose registers • in the instruction add t0, t1, t2, how many registers are read? • how many are written? • are there any instructions that need to read/write more than this? D D D D Q Q Q Q so it's gonna be a component with one input… en en en en and two outputs… etc… with 32(31?) registers inside. Register File (and some other logic and control signals but whatever) CS447

12. The ALU • in MIPS the datapath consists pretty much entirely of the ALU. ALU in all the arithmetic and logic (bitwise) instructions, how many operands are there? + A - ×* ÷* & what kind of operations do we have to be able to do? | ^ ~ << B >> *multiplication and division are kinda weirdos… CS447

13. What's the next instruction? • what order do these instructions run? most instructions change the PC to the next address • print_int: • li v0, 1 • syscall • jrra • lis0, 0 • top: • move a0, s0 • jalprint_int • addis0, s0, 1 • blt s0, 5, top • li v0, 10 • syscall control flow instructions can change the PC to a constant… …or the value from a register… …or one of twochoices, conditionally CS447

14. The program counter and control • the PC is part of the control: it says what step to do next Memory the PC is a memory address Control 0xAC30 PC the memory sends back an instruction 0xC0DE this is an add instruction! the source regs are t0 and t8… the control decodes the instruction and tells everything else what to do but how…? CS447

15. Instruction Execution CS447

16. Phases of instruction execution W M X D F • Fetch(IF or F) • use PC to get the next instruction from memory • Decode(ID or D) • look at the fetched instruction and setcontrol signals • Execute(EX or X) • wait for data to flow through the datapath • Memory Access (MEM or M) • if it's a load or store, do that • Write-back (WB or W) • if there's a destination register, write the result to it often we can do multiple phases "at the same time" CS447

17. Which parts do what PC Control Register File Memory Memory again…I guess? ALU F D W X M CS447

18. Single-cycle machine • we'll be talking about a single-cycle machine and building one for project 2 • this means each instruction takes one clock cycle to execute sbt0, 4(s0) add t0, t1, t2 do F, D, X… do F, D, X… W:store sum in t0 M: store value in memory each instruction ends on the rising edge of the clock (since that's when the registers store their values) CS447

19. The big picture • the overall architecture of a computer looks like this: Inputs Outputs Control Memory ALU Registers Transition Logic State CS447

20. There are lots of states • your whole computer is an FSM :^) • with 4GB RAM, 32 32-bit registers, plus some more registers in there, and all the input/output devices have memory and regs… • we're talking somewhere on the order of uhhhhh 2137438954496 states • it's a finite number of states but it's so ridiculously huge that it's practically infinite • take 1511 to learn about the limits and capabilities of various kinds of computational structures! CS447

21. A Thing about memory CS447

22. ☢️ Structural Hazards ☢️ • how many RAMs does your computer have? one or two? • if we try to do lwt0, (s0)with one memory in a single cycle… Instruction Address Instruction Memory PC Control Load word address…? Loaded word…?? what about sw?!? we can't really do this… memory hardware can't read from two addresses at the same time CS447

23. Von Neumann vs Harvard • one way to solve this problem is to have two memories this is a Harvard Architecture PC Control Register File Instruction Memory Data Memory ALU aVon Neumann Architecture has one memory for both things "Von Neumann" is 2 words for 1 memory… "Harvard" is 1 word for 2 memories… CS447

24. Multi-cycle • a Von Neumann machine has one memory, but uses multiple clock cycles to execute each instruction lwt0, (s0) Cycle 1: Instruction Address Instruction Memory PC Control Loaded word Cycle 2: Load word address multi-cycle machines are by far the most common today but they're more complex… CS447