The SLAC KPiX Chip for ILC GEM-Digital Hadron Calorimetry

1. The SLAC KPiX Chip for ILC GEM-Digital Hadron Calorimetry Andy White for the GEM-DHCAL Group (UTA – UW – CNU) With many thanks to SLAC colleagues: M. Breidenbach, G. Haller, D. Freytag, R. Herbst RD51, Paris, October 2008

2. -2100V ∆V ~400V ∆V ~400V 0V GEM/DHCAL active layer concept

3. KPiX chip One channel of 1024 KPiX/GEM/DHCAL Dynamic gain select 13 bit A/D DHCAL anode pad Storage until end of train. Pipeline depth presently is 4 Leakage current subtraction Event trigger calibration

4. GEM-DHCAL/KPiX boards with Interface and FPGA boards

5. Redesigned chamber – all fishing line spacer • KPiX anode board with extra electronics protection • Better/more direct gas flow through ionization gap • No large dielectric spacer(s) – previously killed signal

6. GEM chamber with KPiX v4 – early 2008

7. GEM + KPiX long source run at SLAC Channel # fC Channel # Channel #

8. GEM + KPiX response in lab at SLAC Right under the source Away from the source Away from the source Right under the source

9. First results from new GEM chamber + KPiX fC scale

10. UTA 75hr Long run at SLAC

11. GEM/DHCAL with KPiX readout • Due to the synchronous design of KPiX, data taking efficiency was low with (asynchronous) source. • KPiX v7 offers new timing flexibility. • Waiting for v7 -> study pedestal subtraction to (eventually) extract MIP distribution • Also study channel variation/stability of calibration and pedestal feedback to SLAC KPiX developers.

12. Calibration studies with KPiX v4 Goals: - understand relation between pedestal distribution and “zero-charge” injected distribution. - investigate stability of gain, response to injected charge, pedestals -> subtraction of noise to yield MIP signals. - understand factors that influence gain etc. (channel to channel, single channel/environment, long-term fluctuations… - ultimately – develop calibration procedure (how often, length of calibration/pedestal runs,…)

13. KPiX injected charge calibration Internal capacitor charged via DAC, readout through data path -> measure gain from slope -> measure “zero-injected charge” response, “Y-int”

14. Initial Calibration Analysis Example • Two Calib Data Sets • 19 hr run starting in evening – weekend – 6/28 • 24 hr run starting in morning - work week – 7/01 • Each Channel’s Pedestal Mean, Sigma; Gain, and Y-Intercept verses Run# (on order of an hour) is graphed for each channel and fit with a straight line. Work of UTA Master’s student Jacob Smith

15. One channel KPiX v4 Ped Sig Gain Y-int Normal Double 17 16 19 18

16. Normal Ped Sig Gain Y-int Double Weekend run 19hr

17. Normal Ped Sig Gain Y-int Double Weekday run 24hr

18. Normal Ped Sig Gain Y-int Double April - June

19. GEM/KPiX source data taking • Issue with KPiX v4 triggering mode: • “forced trigger” (software) mode was used – no fixed time relation between arrival of electron from source and internal timing of KPiX. • - we suspect that a reset is responsible for incomplete integration of the charge • this would distort MIP (Landau) distribution by lowering ADC values - also noise peak wider with data than for pedestal runs -> working on understanding this effect.

20. Next step: KPiX v7 • KPiX is a synchronous device – tied to ILC beam timing • -> problem being efficient in an asynchronous environment e.g. MTBF , cosmics, or source(s). • -> KPiX v4 was only ≤5% efficient for source or asynchronous beam. • -> KPiX v7 allows more flexibility in timing adjustments – via slowing down the master clock - should provide data taking efficiencies in 40-50% range in an asynchronous environment, and has new reset scheme. • First version of v7 now at UTA, plus we have a new anode board designed to work with it. • Initial tests -> calibration with injected charge (internal) -> results.

21. New KPiX Board for v7 1. The KPiX chip is located just next to the PAD area. 2. 310 x 310 mm. with 8 x 8cm. pad area at the centerwith 0.2mm. Gaps between pads. 3. Surface mount parts (connectors...). Nothing will be on the PAD side. 4. All the holes filled for gas tightness. 5. Leaving about 1" space on the edges for sealing.... 6. KPiX board thicker, flatter…

22. KPiX v7 board layout

24. KPiX v7 – first calibration results

25. KPiX v7 chamber plans • New v7 chamber works well – stable (no trips) over several weeks so far. • Verify new software for v7 • Operate v7 with new GEM chamber (in progress) • Complete calibration/understand behavior with v7 • Work with SLAC to achieve 40-50% efficiency in cosmic and source data taking. • Work at UTA and SLAC. • Take beam data at MTBF, CERN?

26. Future Plans for GEM/DHCAL • Complete GEM chamber studies with v7 • Construct ~1m x 0.3m chamber • Construct ~ 1m2 plane(s). • Issue with foil supplier: 3M closed plant in Missouri • Have obtained quotes from CERN for 99cm x 32cm foils. • Alternative: Thick-GEM chamber – if large areas are viable • LCDRD Supplement, 2nd year – minimal amount to purchase foils + limited postdoc support. • Attention to 1m2 plane design – walls/thickness, gas supply, KPiX readout… >>>

27. Future Plans for GEM/DHCAL • Next generation KPiX (256…1024 channels) • Note: started out to test GEM with both KPiX and DCAL chips – we would like to continue this…also perhaps use alternative readout from Europe • …We will have a visitor joining our group in November – much experience with detectors/readout • We also will be hiring a postdoc 50% ILC R&D, 50% ATLAS