A (Active) O (Optional)
Serial data is read in MSB first. Byte/word entries above are shown MSB<->LSB.
Not applicable to Mode 4.
Device treated as an SRAM by the system
Microprocessor treats FPGA as memory mapped I/O.
Simple 24 bit Address and 8 bit Data structure.Cache Logic Mode
32 Bit word defines address and data Information for one byte per clock cycle
31 or 39
Memory Map Pages are all dissociated.
Writing data to one structure has NO impact on any other structure. Key requirement for CacheLogic.
Simple 32 bit interface and 33MHz clocking allow very rapid caching of logic functions.
Symmetrical FPGA architecture results in simple and predictable CacheLogic designs.
Each memory byte has a unique memory map location and can be individually addressed.
Data can be loaded x8 for faster reconfiguration.
In full bitstream, X, Y, Z, Tag information is handled by the on-chip control logic.
Design verification of AT94K FPSLIC devices
Built-in support for Configuration processes
Mode 1AT94K Memory Map and CacheLogic