cms phase 2 tracker r d r lipton 3 27 2014 n.
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CMS Phase 2 Tracker R&D R. Lipton 3/ 27/2014. Module R&D Allocation: Requested ~ $320k, received ~160k Eliminate VICTR testing (continue with FNAL funds and whatever time is available) Eliminate engineering for contributions to the PS chip Eliminate interconnect R&D

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cms phase 2 tracker r d r lipton 3 27 2014
CMS Phase 2 Tracker R&DR. Lipton 3/27/2014

Module R&D Allocation:

  • Requested ~ $320k, received ~160k
    • Eliminate VICTR testing (continue with FNAL funds and whatever time is available)
    • Eliminate engineering for contributions to the PS chip
    • Eliminate interconnect R&D
  • Institutes received 70-80% of requested labor funding, Fermilab about 30%
  • M&S cut by about ½
  • Travel unchanged

- I plan to send this back to Max next week

other items
Other Items
  • US sensor manufacturing was also not funded (in Uli’s proposal). We may try to pursue this through an SBIR or drop the initiative.
  • Additions to the dummy layout:
    • Wafer fiducials and cut lines
    • Chip placement fiducials
flipping the mapsa upside down
Flipping the MaPSA upside down

Nov 2013

Strip sensor

Pixel Sensor

Cooling

…Plus: Cannot get bumped MPAs from TSMC

Because of mixed wire/bump bond requirement

- Why not shift constraint to more flexible sensor producer ?

Proposal

Strip sensor

Extended Pixel Sensor

Cooling

francois.vasey@cern.ch

slide5
TSVs

We had originally planned to collaborate with CERN on the TSV work based on the 3T chip. The vendor doubled his price and we had to drop out of that phase.

I hope to keep this work going in the US, funds are still allocated.

An obvious possibility is to demonstrate insertion of TSVs in the PSI46 chip – which can then be bonded to sensors and tested. This is synergistic with the TSV interests of the phase 2 pixels.

I have written to Jorgen Christianson, Roland Horisberger, Gino Bollaso far with no response…

update on 3d
Update on 3D
  • We received word that processing of the final 3D wafers integrated with sensors is complete at Ziptronix.
  • Although not perfect the process looks encouraging.
    • This was an extremely ambitious process involving three layers of DBI bonded parts.

Excellent alignment

wafer 2 die wafer handle bond
Wafer 2 Die Wafer Handle bond

Ziptronix Proprietary

wafer 2 die to wafer bond
Wafer 2 Die to Wafer bond
  • Ultrasonic microscopy
  • White are bond voids

VICTR

VIPIC

VIP

Ziptronix Proprietary

fpix thoughts
FPIX Thoughts
  • I think that a design based on a simple disk (no turbine blades) should be pursued for phase 2
  • I also think that such a design could also utilized TSVs to great effect, simplifying geometry and assembly.
    • Thermal mismatch between readout PCB and silicon
      • Flex on CF?
  • We could test this with wafers intended for the 3D interposer work

Readout PCB

ROIC

ROIC

sensor

Carbon fiber/carbon foam disk

CO2 cooling

wedges1
Wedges…
  • Wedges are nice but …
    • Need plasma or laser dicing (not a big deal)
    • Require at least 3 different chip variants. At least $200k per mask set for each design
      • Wedge
      • Mirror wedge
      • Rectangle
    • The periphery is hard to manage
      • Chip design tools do not easily accommodate non-Manhattan geometries
      • Central chip has no area for periphery