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PLD Basics

PLD Basics. Agenda. Basic Logic Tutorial Gal / Architecture CPLD / Architecture ISP Software Packaging. Digital Logic Tutorial. Key Poitns. Digital Logic Uses Only Two Values: 1 and 0 1 and 0 usually represent a voltage Example Digital 1 = 5 volts Digital 0 = 0 volts OR

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PLD Basics

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  1. PLD Basics

  2. Agenda Basic Logic Tutorial Gal / Architecture CPLD / Architecture ISP Software Packaging

  3. Digital Logic Tutorial

  4. Key Poitns • Digital Logic Uses Only Two Values: 1 and 0 • 1 and 0 usually represent a voltage • Example • Digital 1 = 5 volts • Digital 0 = 0 volts OR • 1 = ON, 0 = Off • 1 = True, 0 = False

  5. Boolean Basics • Manipulation of digital values is done by Boolean Algebra • Boolean algebra uses primarily AND / OR functions • Boolean equation: TRUE OR FALSE = TRUE • Programmable logic implements the AND / OR functions in hardware

  6. Basic Gates • A gate performs a logic function in hardware • Three basic PLD gate types • AND gates • OR gates • Exclusive-OR (XOR) gates • Gates can have any number of inputs

  7. AND Gate Example • Output of an AND gate is TRUE only if all inputs are TRUE • In a 2 input gate both switches must be on to turn the light on ON OFF OFF OFF OFF OFF ON ON OFF ON ON OFF

  8. Or Gate Example • Output of OR Gate Is TRUE if ANY Input is TRUE • If Either Switch Is ON, The Light Will Trun ON ON OFF OFF OFF ON OFF ON ON OFF ON ON ON

  9. XOR Gate Example • Output of XOR Gate Is TRUE Only of One Input Is TRUE • If Only One Switch Is ON, The Light Will Turn ON ON OFF OFF OFF ON OFF ON ON OFF ON OFF ON

  10. SW1 SW2 SW1 SW2 SW1 SW2 Basic Gates Summary Truth Table (OFF-0, ON-1) Light = SW1 * SW2 Light = SW1 # SW2 Light = SW1 $ SW2

  11. A B D C Input Terms A B C D PLD Symbols • AND Gate Representations • Traditional Representation • PLD Representation • PLD Connections • Hardwired Connection • Programmed Connection • No Connection Made

  12. Typical PLD Structure Input Terms A B C D Product Terms A B C B D Output Output

  13. Registers and Clocks • Registers Store a Digital Value • Values Move From Input To Output With Clock Transition • D = Incoming Data • Q = Outgoing Data • CLK = Clock Input; Causes Data Movement D Q CLK

  14. Typical GAL Logic Structure Input Terms A B C . . . Product Terms Output Enable Registered or Combinatorial D Q Feedback

  15. Macrocell Macrocell Macrocell Macrocell Macrocell Macrocell Macrocell Macrocell Basic GAL Structure Gal Macrocell

  16. GAL Devices • Low density GAL product families: 16/20V8, 18/22V10/26V12, 20RA10, 20XV10, 6001/6002. Families are organized based on architectural layout and a common Output Logic Macro Cell (OLMC). Pin counts and array sizes are all that change across a family. • Lattice GAL devices have Macro Cell counts from 8 to 39 and package sizes from 20 pins to 28 pins. • All GAL devices have registered or combinatorial options, OE control, and selectable output polarity.

  17. GAL Devices • There are also various flavors of each device type. • An L in the product name is a low voltage (3.3V) device. • Zero power devices are either Z or ZD, such as 22LV10ZD. • A VP indicates high drive outputs, such as the 16VP8. • The ispGAL16Z8 was the worlds first ISP PLD. • There is also a Confusion Letter, which roughly indicates the process and technology that the device is based on. • Appended to each device type are speed, power, package, etc. • Device speed grades are by TPD in ns. (HD devices are graded by Fmax in MHz.) • Power dissipation (standard, Low, and Quarter), package type (Pdip, Jlcc, Soic), and Temp/VCC range are appended to device names such as 16LV8C-5LJI for 5nS, low power, PLCC, Industrial.

  18. PAL Vs. GAL • PAL: • Programmable Array Logic. • Registers, feedback paths, dynamic I/O, and both output polarities are available. • There are dozens of different devices each with a fixed architecture. For example, a PAL16H2 has 16 inputs and 2 combinatorial outputs each with 8 PTs per OR gate. Output polarity is positive. • GAL: • Generic Array Logic. • GALs are a superset of PALs. A few GAL devices cover all PAL architectures and hundreds of other possible configurations. • GALs add extremely flexible routing and complete reconfigurability. • The structure of GAL devices allows them to replace many PALs with various IO, input and register counts. Therefore, extra programmable areas known as architecture rows are needed for device configuration. There are global configuration modes and well as individual MacroCell options.

  19. High Density Logic Overview

  20. ispLSI Heritage • The ispLSI Architecture Has Its Origins In The GAL Family • The Best Features Of The GAL Family Have Been Blended Toghter • GAL16V8: Output Logic Macrocell (OLMC) • GAL22V10 More Product Terms • GAL20XV10 Exclusive OR Gate (XOR) • GAL20RA10 Asynchronous Clocking • GAL6002: Input Registers and Product Term Sharing

  21. CPLD Structure Modified Gal Structure Global Routing Pool (Interconnect)

  22. ispLSI Archtiecture Key GAL Features 16V822V1020XV1020RA106002 Prog. Variable XOR Asynch Prod. Term Macrocell Product Clocks Sharing/ Term Input Distribution Registers ispLSI GLB 18XVRA4

  23. High Density Structure • Simple Lattice definition: High Density (HD) devices are those with 1000 or more PLD gates and packages exceeding 28 pins. Our HD devices are Complex PLDs (CPLDs). • HD devices are essentially many identical GAL sized blocks that are repeated to form larger devices. • There is a portion of the device dedicated to routing signals between logic blocks called the Global Routing Pool (GRP) • In GAL terms, the basic GLB (1K, 2K families) is a fancy 18V4. • The logic in the GLB contains most of the features available in the entire GAL family, but on a smaller, more limited scale. • PT clocking • XOR functions • 20 wide OR • PT reset • Much of the logic is mutually exclusive and gets ‘burned’ as other logic is used. This is overcome by having many GLBs.

  24. High Density Structure • Megablock/Megacell based. • A Megablock contains 8 GLBs. • Devices in a family are built from whole Megablocks. • The Global Routing Pool (GRP) is the only means to get signals from one GLB to the next and to get the IO cells to the GLBs. • External pins such as CLK pins, RESET, and GOE are globally fed to all GLBs. • The only other global signals are internally generated clocks and OE’s (differ by family and device).

  25. CPLDs and FPGAs

  26. Field Programmable Gate Arrays Small Logic Building Blocks Register Intensive Distributed Interconnect Slow, Unpredictable, Performance Good at “Narrow Gating” Funcitions Datapath Random Logic High-Density or Complex PLDs Large Logic Building Blocks PLD-Like Ardchitectures Centralized Interconnect Fast Predictable Performance Good at “Wide Gating” Functions State Machines Coutners High Density Logic Overview FPGA HDPLD or CPLD B A C FPGAs and CPLDs Can Compliment One Another In the Same Design!

  27. Major PLD Suppliers FPGAs CPLDs

  28. Technology Comparisons Feature E2CMOS Flash SRAM Antifuse Reprogrammability Yes Yes Yes NO In-System Programmable Yes Yes Yes NO (Volatile) Program Time Fast Med. Fast Slow Erase Time Fast Slow Fast N/A (OTP) Testability Full Full Full Limited External Hardware No No EPROM Pgmr Other Start up Delay

  29. The GDX

  30. (1) IN A IN B Output (0) Control (1 or 0) Mux Register Multiplexer • Commonly called a MUX • An electronic selectable switch • Simplest Form: 2 inputs, 1 output, and 1 control • GDX(V) Building blocks: 4 inputs, 1 output, 2 control

  31. I/O Cell Bank D ISP Control Global Routing Pool (GRP) I/O Cell Bank A I/O Cell Bank A Boundary Scan Control I/O Cell Bank B ispGDX/V Functional Diagram • Simmilar to CPLD • Centralized Routing Pool • Consistent timing • Non Volatile • Registers available on output • Small ammounts of logic possible • Specialized Functionality • Dynamic routing of signals • No dedicated logic

  32. C A A A Sel1 Sel0 B A B B B 1 1 Sel0 A C A to C Pt X 0 X A X 1 B X 0 X X A 1 X B X P T S A 1 1 B B to C D C A to D P TSA D B to D • One PT Per Input Port • One Macrocell Per Output Port BFW in Crosspoint Switch Application CPLD Implementation System-level Representation (2 X 2) x 1 bit Switch Logical Representation D Sel1 GDX/V Implementation • One Mux Input Per Input Port • 4 Input Ports Max. Per GDX • 16 Input Ports Max. Per GDXV • One I/O Cell Per Output C Sel0

  33. Input Registers 1 Channel 1 4:1 MUX Channel 2 Channel 3 Channel 4 5 Channel 5 Channel 6 4:1 MUX Channel 7 Channel 8 1…16 4:1 MUX 9 Channel 9 Channel 10 4:1 MUX Channel 11 Channel 12 Channel 13 Channel 14 4:1 MUX Channel 15 16 Channel 16 Telecom Aplications (PDP) • Multiplex 16 Slow-Speed Channels Into A Single High-Speed Channel • 1 Level in GDXV Register Bypass

  34. Mem ASIC ASSP CPU BUS I/F Crosspoint Switching Application Backplane Controller • 8000/V • 5000V • 2000E/VE Functions Performed: • Cross Connect Data From One Source To Another • Perform Arbitration • Generate Switching Control • GDX/V Control Backplane Line Card Line Card Line Card Line Card Line Card • 8000/V • 5000V • 2000E/VE Control Switch Controller • GDX/V Line Card Line Card Line Card Line Card

  35. In-System-Programmable(ISP)

  36. Historical Programming Originally all programming had to be done in a separate piece of hardware • One Time Programmable (OTP) • Antifuse technology • Not erasable • Erasable PLDs (EPLDs) • UV light used to erase device • Expensive packaging • Electrically Erasable PLDs • Could be erased by programming equipment • Had to be removed from circuit for both programming and erasing • Uses High (~12v) voltages to program

  37. In-System-Programming • ISP PLDs • Programming and erasing done through a wire interface to the part • Programming voltages generated “on chip” • Part can be soldered to the board • No need to handle parts • More delicate (smaller) packaging can be used • Field upgrades are possible • Multiple / different devices can be programmed at once

  38. SDO 5-wire Lattice ISP SDI Programming MODE SCLK Interface ispEN ispGAL ispGDS ispLSI ispLSI 22V10 22 2032 1032E Two ISP programming algorithms • Lattice ISP • Invented by Lattice • Five wire interface • Three state state-machine

  39. TDO 4-wire ispJTAG TDI Programming TMS Interface TCK VCC BSCAN/ispEN ispEN Non-Lattice ispLSI ispLSI BSCAN 2032V 3256A Device ISP Functionality • JTAG / Boundary Scan • Pseudo standard across vendors • Four wire interface • 16 state state-machine

  40. 5-wire Lattice ISP and TDO/SDO TDI/SDI ispJTAG Mixed TMS/MODE Programming TCK/SCLK ispEN Interface ispLSI ispLSI ispLSI 1032E 2032 2128 VCC BSCAN/ispEN ispEN Non-Lattice ispLSI ispLSI BSCAN 2032V 3256A Device Mixed Programming • Mixed Programming • JTAG and Lattice ISP are incompatable if used is the same chain (in series) • Parallel sharing of signals is possible

  41. ISP InnovatorandMarket Leader

  42. Lattice introduces Cell Based PLD with Memory Lattice introduces the ISP GAL ispLSI 1000 1999 1986 1996 1997 1985 1992 TODAY Lattice Invents the ISP PAC Programmable Analog Lattice invents the ISP CPLD Lattice invents the GAL Architecture; introduces E2CMOS Lattice Introduces the ISP Generic Digital Crosspoint Industry Shaping Innovations

  43. Historical Market Overview • Circa 1985 Lattice GAL22V10 • Circa 1990 Xilinx 3042 • Circa 1993 Altera 7032, 7128 • Circa 1996 Altera/Xilinx 10K/4000 • Circa 1998 Lattice BFW 2KVE, 5KV, 8KV

  44. Company Background • Lattice is the Inventor of In-System-Programmable PLDs • The PLD Performance Leader • World’s Largest Supplier of ISP PLDs • Fastest Growing CPLD Supplier • Broadest Line Supplier

  45. Lattice Device Packages

  46. Space-SavingPackages With ISP Devices Plastic BGA Plastic QFP TQFP SuperBGA SSOP ISP Enables the Use Of Space-Saving TQFP & BGA Packages!

  47. Lattice Packaging Roadmap QFP (.50-.80mm) 3.5 Plastic BGA (1.27mm) 3.0 2.5 2.0 Package Thickness (mm) FinePitch BGA (1.0mm) 1.5 ChipArray BGA (.50-.80mm) TQFP (.40-.80mm) 1.0 Super BGA (1.27mm) 0.5 (.xxmm) = Lead Pitch 1992 1994 1996 1998 2000 2002 YEAR

  48. Software Basics

  49. Start To Finish Concept Design Entry Schematic or HDL Design Synthesis 3rd Party Tools or Lattice Place and Rout Lattice Fitter Download to Part

  50. a b Design Entry Methods • Schematic is used to capture structural models using IC vendor-supplied logical gates and other macro functions • Used for designing PLDs, CPLDs, FPGAs, and ASIC • HDL (Behavioral) models differ from structural models in that there is no one-to-one correspondence between expressions and logic gates • Enables programmable description of circuits and systems Schematic HDL .. process begin carry <= (a and b); sum <= (a xor b); end process;

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