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Exclusive Test and its Application to Fault Diagnosis

Exclusive Test and its Application to Fault Diagnosis. Vishwani D. Agrawal Dong Hyun Baik Yong C. Kim Kewal K. Saluja. Overview. Problem Statement Introduction Background on Diagnosis Definitions for Diagnosis Main Idea Exclusive Test Example of Exclusive Test

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Exclusive Test and its Application to Fault Diagnosis

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  1. Exclusive Test and its Application to Fault Diagnosis Vishwani D. Agrawal Dong Hyun Baik Yong C. Kim Kewal K. Saluja

  2. Overview • Problem Statement • Introduction • Background on Diagnosis • Definitions for Diagnosis • Main Idea • Exclusive Test • Example of Exclusive Test • Exclusive Test Generation • Properties of Exclusive Test • Diagnosis Method • Results • Conclusion Agrawal, Baik, Kim and Saluja: VLSI Design 2003

  3. Problem Statement • Obtain high resolution diagnostic test using a single-fault ATPG. Agrawal, Baik, Kim and Saluja: VLSI Design 2003

  4. Introduction: Background on Diagnosis • Single-fault dictionary approaches • Simulation based: Chang et al. Fault Diagnosis of Digital Systems, NY, Wiley-Interscience, 1970 • Most common method for diagnosis • Diagnostic test pattern generation: Specialized ATPGs • Implication based: Gruning et al. DIATEST: A Fast Diagnostic Test Pattern Generator for Combinational circuits - ICCAD, 1991 • Multiple-pass strategy: Savir et al. - Testing for, and Distinguishing between Failures - FTCS, 1982 Agrawal, Baik, Kim and Saluja: VLSI Design 2003

  5. s-a-1 s-a-1 • Diagnostic Resolution (DR). test syndrome for fault g0 • DR = No. of faults (classes) • No. of syndromes • A measure of quality of diagnosis Introduction: Definitions for Diagnosis • Consider CUT on the right • All 10 faults are detected by 5 test vectors: T1 = 001, T2 = 010, T3 = 011, T4 = 101, T5 = 111 • Diagnostic dictionary Add T6 = 000 • DR = 10/9=1.11 • 10 Faults, but only 9 syndromes: b1 and d1 cannot be distingushied • DR = 10/10=1.00 • 10 syndromes: b1 and d1 are now distinguished Agrawal, Baik, Kim and Saluja: VLSI Design 2003

  6. Main Idea • Exclusive test • An Input vector that detects only one fault from a pair of targeted faults at a primary output • C0: A fault free circuit • C1: CUT with fault f1 • C2: CUT with fault f2 Agrawal, Baik, Kim and Saluja: VLSI Design 2003

  7. s-a-1 s-a-1 Example of Exclusive Test • Application • Generate an additional vector to improve diagnostic resolution: distinguish a pair of faults, b1 and d1. • Example • Diagnostic dictionary T6 = 000

  8. 0 0 0 D Exclusive Test GenerationKim, Agrawal and Saluja - “Multiple Faults: Modeling, Simulation and test” VLD 2002 Exclusive test for (b1,d1), T6 = 000 b1 d1 Agrawal, Baik, Kim and Saluja: VLSI Design 2003

  9. Properties of Exclusive Test • If there exists an exclusive test two faults then they can be distinguished from each other by using that test. • If no exclusive test exists then the faults cannot be distinguished; two faults form an equivalent fault set. Agrawal, Baik, Kim and Saluja: VLSI Design 2003

  10. Start with fault detection tests Done Is DR satisfactory? Generate an exclusive test for an undiagnosed fault pair Form an equiv. Fault set Diagnosis Method Make dictionary and isolate undiagnosed fault sets Yes No No Yes Test exists? Append the test ATPG aborted Agrawal, Baik, Kim and Saluja: VLSI Design 2003

  11. Results: Model • For illustration, an XOR-tree is added to the output of the circuit under test to make it a single output circuit. • We use * to denote a modified circuit with a single output XOR-tree at its outputs. • General multiple-PO case is discussed later. Agrawal, Baik, Kim and Saluja: VLSI Design 2003

  12. Test Generation−ISCAS85 Circuits Agrawal, Baik, Kim and Saluja: VLSI Design 2003

  13. Diagnostic Results−ISCAS85 Circuits

  14. Test Generation−c432 Agrawal, Baik, Kim and Saluja: VLSI Design 2003

  15. Diagnostic Results−c432 C432: Simulated using tests derived with c432*, then targeted only undiagnosed faults

  16. Conclusion • Definition of an exclusive test and an ATPG method are introduced. • A comprehensive exclusive test based diagnostic method is presented where a conventional single fault ATPG can be used. • Results for ISAS85 benchmark circuits are presented. Agrawal, Baik, Kim and Saluja: VLSI Design 2003

  17. s-a-1 s-a-1 s-a-0 s-a-0 s-a-1 Multiple (4) stuck-at fault Equivalent Single Stuck-at fault Supplement 1: Multiple Fault Model • Kim, Agrawal and Saluja - • “Multiple Faults: Modeling, Simulation and test” - VLSI Design,2002 • Convert multiple fault test generation problem into single fault test generation problem. Agrawal, Baik, Kim and Saluja: VLSI Design 2003

  18. Supplement 2: Test Generation−ISCAS85 Circuits Agrawal, Baik, Kim and Saluja: VLSI Design 2003

  19. Supplement 3: Diagnostic Results−ISCAS85 Circuits

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