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CS 151 Digital Systems Design Lecture 28 Timing Analysis

CS 151 Digital Systems Design Lecture 28 Timing Analysis. Overview. Circuits do not respond instantaneously to input changes Predictable delay in transferring inputs to outputs Propagation delay Sequential circuits require a periodic clock

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CS 151 Digital Systems Design Lecture 28 Timing Analysis

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  1. CS 151Digital Systems DesignLecture 28Timing Analysis

  2. Overview • Circuits do not respond instantaneously to input changes • Predictable delay in transferring inputs to outputs • Propagation delay • Sequential circuits require a periodic clock • Goal: analyze clock circuit to determine maximum clock frequency • Requires analysis of paths from flip-flop outputs to flip-flop inputs • Even after inputs change, output signal of circuit maintains original output for short time • Contamination delay

  3. Clock Period Clock Sequential Circuits • Sequential circuits can contain both combinational logic and edge-triggered flip flops • A clock signal determines when data is stored in flip flops • Goal: How fast can the circuit operate? • Minimum clock period: Tmin • Maximum clock frequency: fmax • Maximum clock frequency is the inverse of the minimum clock period • 1/Tmin = fmax

  4. A Y t c d t p d Combinational Logic Timing: Inverter A Y • Combinational logic is made from electronic circuits • An input change takes time to propagate to the output • The output remains unchanged for a time period equal to the contamination delay, tcd • The new output value is guaranteed to valid after a time period equal to the propagation delay, tpd

  5. Combinational Logic Timing: XNOR Gate • The output is guaranteed to be stable with old value until the contamination delay • Unknown values shown in waveforms as Xs • The output is guaranteed to be stable with the new value after the propagation delay

  6. Combinational Logic Timing: complex circuits Tpd = 2ns Tcd = 1ns Circuit X Tpd = 3ns Tcd = 1ns A C A Circuit X C B Tpd = 5ns Tcd = 1ns B • Propagation delays are additive • Locate the longest combination of tpd • Contamination delays may not be additive • Locate the shortest path of tcd • Find propagation and contamination delay of new, combined circuit

  7. Clocked Device: Contamination and Propagation Delay D Clk Q t cd t Clk-Q • Timing parameters for clocked devices are specified in relation to the clock input (rising edge) • Output unchanged for a time period equal to the contamination delay, tcd after the rising clock edge • New output guaranteed valid after time equal to the propagation delay, tClk-Q • Follows rising clock edge

  8. Clocked Devices: Setup and Hold Times ts th D Clk Q • Timing parameters for clocked devices are specified in relation to the clock input (rising edge) • D input must be valid at least ts(setup time) before the rising clock edge • D input must be held steady th(hold time) after rising clock edge • Setup and hold are input restrictions • Failure to meet restrictions causes circuit to operate incorrectly

  9. Edge-Triggered Flip Flop Timing D CLK th = hold time ts = setup time • The logic driving the flip flop must ensure that setup and hold are met • Timing values (tcd tpd tClk-Q ts th)

  10. TClk-Q = 5 ns Ts = 2 ns Tpd = 5ns TClk-Q = 5ns X Y D Q D Comb. Logic Z Q D FFB FFA G CLK Analyzing Sequential Circuits • What is the minimum time between rising clock edges? • Tmin = TCLK-Q (FFA) + Tpd (G) + Ts (FFB) • Trace propagation delays from FFA to FFB • Draw the waveforms! Fmax = _______

  11. Tpd = 4ns Q D Comb. Logic F Q D X Y Comb. Logic H Z FFB FFA Tpd = 5ns CLK TClk-Q = 5ns TClk-Q = 4 ns Ts = 2 ns Analyzing Sequential Circuits • What is the minimum clock period (Tmin) of this circuit? Hint: evaluate all FF to FF paths • Maximum clock frequency is 1/Tmin

  12. Tpd = 4ns Q D Comb. Logic F Q D X Y Comb. Logic H Z FFB FFA Tpd = 5ns CLK TClk-Q = 5ns TClk-Q = 4 ns Ts = 2 ns Analyzing Sequential Circuits Fmax = _______ • Path FFA to FFB • TClk-Q(FFA) + Tpd(H) + Ts(FFB) = 5ns + 5ns + 2ns = 12ns • Path FFB to FFB • TCLK-Q(FFB) + Tpd(F) + Tpd(H) + Ts(FFB) = 4ns + 4ns + 5ns + 2ns

  13. Q D Q D Analyzing Sequential Circuits: Hold Time Violation Th = 2 ns Tcd = 2ns Tcd = 1ns X Y D Comb. Logic Z FFB FFA G CLK • One more issue: make sure Y remains stable for hold time (Th) after rising clock edge • Remember: contamination delay ensures signal doesn’t change • How long before first change arrives at Y? • Tcd(FFA) + Tcd(G) >= Th • 1ns + 2ns > 2ns

  14. Tcd = 1ns Q D Comb. Logic F Q D X Y Comb. Logic H Z FFB FFA Tcd = 2ns CLK TClD = 1ns TClD = 1 ns Th = 2 ns Analyzing Sequential Circuits: Hold Time Violations All paths must satisfy requirements • Path FFA to FFB • TCD(FFA) + TCD(H) > Th(FFB) = 1 ns + 2ns > 2ns • Path FFB to FFB • TCD(FFB) + TCD(F) + TCd(H) > Th(FFB) = 1ns + 1ns + 2ns > 2ns

  15. Summary • Maximum clock frequency is a fundamental parameter in sequential computer systems • Possible to determined clock frequency from propagation delays and setup time • The longest path determines the clock frequenct • All flip-flop to flip-flop paths must be checked • Hold time are satisfied by examining contamination delays • The shortest contamination delay path determines if hold times are met • Check handout for more details and examples.

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