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378 - MIPS instruction encoding

378 - MIPS instruction encoding

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378 - MIPS instruction encoding

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  1. 378 - MIPS instruction encoding From symbols to bits

  2. A simple architecture

  3. Instruction encoding

  4. op rs rt rd shamt funct R format • Instructions, like registers and words of data, are 32 bits long • Arithmetic Instruction Format (R format): add $t0, $s1, $s2 op 6-bits opcode that specifies the operation rs 5-bits register file address of the first source operand rt 5-bits register file address of the second source operand rd 5-bits register file address of the result’s destination shamt 5-bits shift amount (for shift instructions) funct 6-bits function code augmenting the opcode

  5. Memory . . . 0001 1000 + . . . 1001 0100 . . . 1010 1100 = 0x120040ac 2410 + $s2 = 0xf f f f f f f f 0x120040ac $t0 0x12004094 $s2 op rs rt 16 bit offset 0x0000000c 0x00000008 0x00000004 0x00000000 data word address (hex) Machine Language - Load Instruction • Load/Store Instruction Format (I format): lw $t0, 24($s2)

  6. op rs rt 16 bit offset • MIPS conditional branch instructions: bne $s0, $s1, Lbl #go to Lbl if $s0$s1 beq $s0, $s1, Lbl #go to Lbl if $s0=$s1 • Ex: if (i==j) h = i + j; bne $s0, $s1, Lbl1 add $s3, $s0, $s1Lbl1: ... • Instruction Format (I format): • How is the branch destination address specified?

  7. Lab 1: Due April 24thCheck point April 17th 378: port your Strcpy 378-HW: port Strcpy AND Make a light Blink in “slowly”

  8. What is an FPGA?

  9. What can you do with an FPGA? • Emulate most circuits with about a factor of 10X slow down to full custom (that’s still 100mhz!) • Largest FPGAs can hold ~ 8M gates. Pentium = 5M, Pentium4 = 44M

  10. What can’t you do with FPGAs • Content addressable memories • Memories with more than 1 write port. • Somethings are do-able, but large: • arbitrary barrel shifters • Dividers / multipliers • Floating point (see shifters)

  11. Tool flow • Turn-in: Design, Waveforms, functional simulation output Active HDL 378: • Turn-in: Design, Waveforms, functional simulation output Active HDL 378-HW: downloader Symplicty ISE tools Impact Verilog -> netlist Netlist -> FPGA XUP board Demonstrate it working