Staticroute a novel router for the dynamic partial reconfiguration of fpgas
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StaticRoute : A novel router for the dynamic partial reconfiguration of FPGAs. Brahim Al Farisi , Karel Bruneel, Dirk Stroobandt. Overview. Dynamic reconfiguration of FPGAs: Modular d ynamic reconfiguration (MDR) Dynamic circuit specialization (DCS) Novel tool flow

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Staticroute a novel router for the dynamic partial reconfiguration of fpgas

StaticRoute: A novelrouter forthe dynamicpartialreconfiguration of FPGAs

Brahim Al Farisi,

Karel Bruneel, Dirk Stroobandt


Overview
Overview

  • Dynamic reconfiguration of FPGAs:

    • Modular dynamic reconfiguration (MDR)

    • Dynamic circuit specialization (DCS)

  • Novel tool flow

  • Experiments and results

  • Conclusions


FPGA

FF

LUT

0

0

1

0

0

0

1

0

0

1

1

0

0

1

0

1

1

1

1

0

0

1

1

0

0

0

0

0

0

1


Conventional fpga tool flow
Conventional FPGA tool flow

HDLdesign

SYNTHESIS

MAP

PLACE

ROUTE

Configuration

Input: textual description of functionality


Textual description hdl design
Textual description: HDLdesign

in0

entity multiplexer is

port(

sel : in std_logic_vector(1 downto 0);

in : in std_logic_vector(3 downto 0);

out : out std_logic

);

end multiplexer;

architecture behavior of multiplexer is

begin

out <= in(conv_integer(sel));

end behavior;

in1

out

in2

in3

sel0

sel1


Conventional fpga tool flow1
Conventional FPGA tool flow

HDLdesign

SYNTHESIS

MAP

100101

011100

001111

PLACE

ROUTE

Configuration

Input: Textual description of functionality

Output: FPGA configuration


Dynamic reconfiguration of fpgas
Dynamic reconfiguration of FPGAs

M3

M3

M1

M1

M2

M2

  • Advantages:

    • Smaller area

    • Lower power usage

  • Disadvantage:

    • Reconfiguration time

  • Goal: area reduction with reduced reconfiguration time


Dynamic reconfiguration of fpgas1
Dynamic reconfiguration of FPGAs

M3

M3

M1

M1

M2

M2

  • 2 tool flows:

    • Modular Dynamic Reconfiguration (MDR)

    • Dynamic Circuit Specialization (DCS)


Modular dynamic reconfiguration mdr
Modular Dynamic Reconfiguration (MDR)

Mode 1

Mode 2

SYNTHESIS

SYNTHESIS

MAP

MAP

PLACE

PLACE

ROUTE

ROUTE

Configuration 1

Configuration 2


MDR

  • Different modes are implemented independently

  • Complete area is rewritten

     Results in long reconfiguration times


Dynamic circuit specialization
Dynamic Circuit specialization

  • Design with parameters: input signals that only change once a while

  • Implement dependency on parameters using dynamic reconfiguration


Dynamic circuit specialization1
Dynamic circuit specialization

Param. HDL

SYNTHESIS

TMAP

TPLACE

TROUTE

Param. Conf.

Input: annotatedtextual description of functionality


Parameterised hdl design
Parameterised HDL design

entity multiplexer is

port(

--BEGIN PARAM

sel : in std_logic_vector(1 downto 0);

--END PARAM

in : in std_logic_vector(3 downto 0);

out : out std_logic

);

end multiplexer;

architecture behavior of multiplexer is

begin

out <= in(conv_integer(sel));

end behavior;

in0

in1

out

in2

in3

sel0

sel1


Dynamic circuit specialization2
Dynamic circuit specialization

Param. HDL

SYNTHESIS

TMAP

TPLACE

TROUTE

Param. Conf.

Input: Annotatedtextual description of functionality


Dynamic circuit specialization3
Dynamic circuit specialization

Param. HDL

SYNTHESIS

TMAP

1A0101

0111B0

0C1111

A= sel0AND sel1

B= sel1

C= sel0OR sel1

TPLACE

TROUTE

Param. Conf.

Input: Annotatedtextual description of functionality

Output: Parameterised configuration



Dynamic circuit specialization4
Dynamic Circuit Specialization

  • Reduced reconfiguration time

  • Takes as input 1 parameterised design

  • How to implement several modes with DCS?


Goal of our research
Goal of our research

  • Develop tool flow for dynamic reconfiguration of multi-mode circuits

  • Reduce reconfiguration time

  • Combined routing of different modes using TRoute:

     Increase correlation between configurations of the different modes


Novel tool flow
Novel tool flow

Mode 1

Mode 2

SYNTHESIS

SYNTHESIS

MAP

MAP

PLACE

PLACE

ROUTE

ROUTE

Merge

Configuration 1

Configuration 2

TROUTE

Param. Conf.


Experiments
Experiments

  • Regular expression matching hardwareand general MCNC benchmarks

  • Circuits of 200-400 LBs

  • 2 to 5 modes considered

  • Comparison of MDR and DCS (this work)

  • Metrics:

    • Reconfiguration time

    • Wire length (of each mode separately)


Results reconfiguration time
Results – Reconfiguration time

  • Speed-up of routing reconfiguration time

  • Speed-up of total reconfiguration time





Conclusions
Conclusions

  • Using novel tool flow that uses TRoute:

    • Total reconfiguration speed-up of 3X to 5X

    • Increase in wire length between 10 to 25 percent


A novel tool flow for increased routing configuration similarity in multi mode circuits

A noveltool flow forincreased routing configurationsimilarity in multi-mode circuits

Brahim Al Farisi,

Elias Vansteenkiste, Karel Bruneel, Dirk Stroobandt


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