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Electronics

Electronics. Diego Real Máñez. SC Amsterdam 05 de November de 2013. l. PSEUDO OCTOPUS. 8 Pseudo Octopus designed by Bologna Independent stimuli for every TDC channel To be produced by Bologna To be ready by end N ovember / beginning December 6 Pseudo Octopus designed by Saclay

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Electronics

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  1. Electronics Diego Real Máñez SC Amsterdam 05 de November de 2013

  2. l PSEUDO OCTOPUS • 8 PseudoOctopusdesignedbyBologna • Independentstimuliforevery TDC channel • To be producedbyBologna • To be readybyendNovember / beginningDecember • 6 PseudoOctopusdesignedbySaclay • To be producedbyDemokritos • GerbersalreadysendbySaclaytoDemokritos • Someproductionquestionsstillto be solvedbySaclay • Somedelayin theproduction

  3. l PowerBoardsPrototypes • 10 boardsto be produced • PCBsalready in Demokritos • ExpectedbyendNovember

  4. l CLBv2 Prototypes • Layoutto be finishsoon -> Nextweek • To be produced 6 protos: • 2 protos in MASER • 4 protos in PHOENIX • Expectedbymid-december

  5. l Preserie 1 • CLBv2 • Quantity and FPGA to be decided: • 25 or 50 • 325T or 160T • Ongoingtestsin Valencia tocheck FPGA resourcesconsumption in both cases (To be presentedonthenext CLB meeting) • CostStimation(Betterstimationwhengerberssentto MASER and PHOENIX): • 25 boards -> 20 000 € + FPGAs (325 T : 15 000 € - 160T: 5000 € ). Total between 25000 - 35000 € • 50 boards -> 35 000 € + FPGAs (325 T : 30 000 € - 160T: 10000 € ). Total between45000 - 65000 € • Delivery time fortheFPGAs: 2 month • Startproduction: EndMarch (FPGAsto be orderedbyJanuary) • Delivery: EndApril • POWER BOARD • To be managedbyDemokritos-> Price stimation130 € / Powerboard

  6. l FIRMWARE: WR (8 ns) + IPMUX 31 TDCs IP/UDP Packet Buffer Stream Selector (IPMUX) Start Time Slice UTC & Offset counter since Fifo TDC0 Time Slice Start RxPort 1 RxPacket Buffer 64KB 31 PMTs RxPort 2 Fifo TDC 30 Rx Stream Select Rx_mac2buf Rx_mac2buf Rx_buf2data Flags RxPort_m Management & Control S aux_master State Machine Management & Config. 6 1 7 Pause Frame 5 ADC 0 Fifo 4 Hydrophone 2 3 TxPacket Buffer 32KB TxPort 1 Management & Control TxPort 2 S Tx Stream Select Tx_pkt2mac Tx_pkt2mac Tx_data2buf Multiboot 0 1 Done! Flags 2 TxPort_m S Management & Control Nano Beacon S ext_wb M M M M S M M M M M Debug LEDs WB Crossbar (1x8) WB Crossbar (3x2) S S S S S M M M GPIO I2C 2nd CPU LM32 I2C SPI UART Xilinx Kintex-7 S MEM S M S M Data UTC time & Clock (PPS, 125 MHz) Compass Debug RS232 Temp Tilt SPI Flash Control Point to Point interconnection Wishbone bus

  7. l FIRMWARE: WR • Currently: • WR (8 ns) : -> data extraction • ◦ Intregrating/ Connecting LM32_2nd (WR + IPMUX + LM32) • WR (1 ns) : • ◦ Soft PLL (hardware + software) • ◦ Calibration procedure • ◦ PPS generator • To do (in order of priority): • WR (1 ns) : • ◦ Mini-nic <= Complex, but seems to work (no further action at the moment) • ◦ SysCon <= easy (no further action at the moment) • ◦ LM32 debugger

  8. l CLBv2: Other software & firmware issues • Preparation of CLBv2 test in Genova: • Using UART for data extraction • Preparation of a Java GUI for TDC data presentation • (Possibility to connect latter to the Ethernet port and to WR) • Ethernet development advancing in Bologna + Test of the WR spec board • Software development (SPI embedded driver + java GUI) in Valencia to test the SPI flash writing (reconfigurability) • Embedded software (Need of another Software engineer!) • Firmware integration already started in Valencia (LM32 + State Machine + TDC + watchdog + multiboot) • Purchasing in Valencia all the material to have a replica of the current WR network in Nikhef

  9. l CLBv2: FPGA resources - preliminary • Resourcesused so far (WR+ IPMUX + TDC(2048 hits)+State Machine) • (KC705 => Kintex7-325): • Number of Slice Registers: 18,530 out of 407,600 5% • Number of Slice LUTs: 22,591 out of 203,800 11% • Number of Bonced IOBs: 130 out of 500 26% • Number of RAMB36E1: 133 out of 445 30% • Number of RAMB18E1: 48 out of 890 5% • Number of BUFG/BUFGCTRLs: 10 out of 32 31% • Number of MMCME2_ADVs: 4 out of 10 40% Resourcesused so far (WR+ IPMUX + TDC(2048 hits)+State Machine) (Kintex7-160T): Number of Slice Registers: 18,530 out of 202800 9% Number of Slice LUTs: 22,591 out of 101,400 22% Number of Bonced IOBs: 130 out of 400 33% Number of RAMB36E1: 133 out of 325 41% Number of RAMB18E1: 31 out of 650 7% Number of BUFG/BUFGCTRLs: 10 out of 32 31% Number of MMCME2_ADVs: 4 out of 8 40%

  10. l ON-SHORE STATION: TOPOLOGY I 200 Mbits / sec

  11. l ON-SHORE STATION: TOPOLOGY II • GPS signaldistributedtoallthe WR switches. Problems: • number of connections • the fanoutlayout • cable distances • enviromentalconditions of the cables (temperature, pressure) • can have a strong impact in the accuracy and precision of the GPS signal

  12. l ON-SHORE STATION: BROADCAST • Both approach can be implemented with the same physical topology. Thus, in order to not dismiss any approach at this stage, 7S proposal for broadcast development process is: • Step 1: Implement a physical topology network • where data and sync(WR net) are split at level 2. • Step 2: Implement modifications of SW/GW taking • “same clock” in all switches for granted: • - Modification of WR PTP packet. (MAC destination) • PTP packet propagation from WRS to WRS Grand Master or vice versa. • Study precision and accuracy of the signal according to KM3Net req. • (until now both topology I and II are practically the same. This is the end of topology II) • Step 3: If requirements are not met, then, Transparent clock protocol is implemented in WRSs so that the precision and accuracy is improved by taking into account the different clocks and levels of the network.

  13. l ON-SHORE STATION: BROADCAST Step 1: Network Topology T1 T4 RT2 T4, PhMM PhMM,RT 1 Step 2: Broadcast implementation Step 3: Transparent clock implementation

  14. l ON-SHORE STATION: BROADCAST The Transparent Clock approach is the most efficient, nevertheless, we will study the necessity of its implementation as we fulfill KM3Net timing requirements. Milestone 1: It will include the basic developments and modifications on the WR switch SW/GW to be able to implement a broadcast proof of concept. This first stage will provide an estimation on signal precision and accuracy with the new topology as well as the suitability of the broadcast channel within the KM3Net optical network. Deadline: 15 of December Milestone 2: It will improve and optimize the GW/SW of the customized WR switch as well as implement the modifications needed to finish the broadcast channel, verification and validation tests, calibration packets... taking into account the KM3Net timing requirements. Deadline: End of January Demostratorneeded!

  15. l RELIABILITY • SthepaneColognesfrom APC isgoingtoperformanstudy of Reliabilityfor: • Octopusv3 • PowerBoard • CLBv2 • Also he isgoingto prepare a ReliabilityGuidelinefor KM3NeT (veryuseful at thepreseriestep) • (Forthemomenttheguidelinefor CTA has beendistributedtorelevantpeople)

  16. l OCTOPUSv3 • Adapt octopus V2 • • reduce EMI (piezo sensor integration) • • fit piezo sensor piggy-back board • • allow long-term operations • KVI alreadypreparingmassproduction: • 55 boardbyfebruary 2014 • 635 boardsbySeptember 2014 • KVI preparingthepurchase of allthe Octopusv3 connectors • And CLBv2 counterpartconnectors (Genovaisalsopurchasingsome of theseconnectors)

  17. PLANNING http://ific.uv.es/~real/CLB/CLBv2_%20Planning_Nov_2013.pdf

  18. BACKUPS

  19. WR SWITCHES AT THE BASE OF THE CONTAINERS Switch at the base of the D.U. 1.- Modification of the switch (industrial components) -> Same behaviour as current switch (for testing the CLBv2 the current switch can be used) 2.- Modification of the Base Container to allocate the switch 3.- 20 ports switch at the base of the D.U Can be skipped with D.U. of 16 nodes10 GB Switch on the on-shore station Great modification of the firmware/software at the WR switch. 1 year development

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