System-Level Design Methods for Low-Energy Architectures Containing Variable Voltage Processors

1. System-Level Design Methodsfor Low-Energy Architectures Containing Variable Voltage Processors Flavius Gruian <Flavius.Gruian@cs.lth.se> Embedded Systems Design Laboratory Lund Institute of Technology

2. Presentation Outline • Problem Description • Our view of an energy efficient system-level design flow • Two Approaches: • Speed-up and Stretch • Eye-on-Energy • Experiments • Conclusion PACS2000

3. Task Energy The task executes all its N cycles at V1: E = NEV1 The task executes partly at V2 and partly at V3: E = xEV2 + (N-x)EV3 Task Execution Time Energy vs. Delay on Variable Supply Voltage Processors Sample characteristics fora three supply voltage processor PACS2000

4. Task-graph bus P1 P2 Single Vdd P2 P1 bus bus P2 P2 P1 P1 Dual Vdd case Scheduling on Variable Supply Voltage Processors Design problem: minimize E while keeping the deadline Ideal case PACS2000

5. minimize energy under time and resource constraints Specification(task-graph) Constraints(deadline) ResourcePool Generate Assignment [Simulated Annealing] Focus on Low Energy Schedule explore Evaluate • tightly coupled assignment and scheduling satisfactory Assigned & Scheduled Task-Graph System-Level Design Flow for Low Energy PACS2000

6. Simulated Annealing for Assignment Why SA? • classic heuristic, easy to implement • highly tunable Implementation issues: • neighborhood: random(task).processor = random(processor) • cost: • quality measure of the final step solutions • fast to compute (ms) PACS2000

7. ad hoc method minimize the schedule length in the assignment step list-scheduling with critical-path priority as a core scheduling technique the schedule is scaled in the final step Generate Assignment SACost function:Schedule length List-SchedulingPriority: CP Schedule andStretch The “Speed-up and Stretch” Design Flow • conventional design algorithms • no information about the energy until the end! PACS2000

8. LEneS: Low-Energy Scheduling • list-scheduling • energy consumption as priority • dynamic priority recalculation • loose deadlines: scales the tightest schedule • tight deadlines: stretches tasks from the non-critical path whenever possible • uses energy information • too slow to be used in a SA loop PACS2000

9. uses estimated energy as feedback not much more time consuming than S&S indirect feedback - estimates special scheduling method Tune the Estimator Generate Assignment SACost function:Estimated Energy ScaledLEneS Schedule The “Eye-on-Energy” Design Flow PACS2000

10. EonE: The Energy Estimator • a, b, and c: • task-graph dependent • tuned by regression • fast evaluation (slowest is Tmin) • under 10% avg. deviation from E final values Deadline Load Processor Energy Load Eest = a(Emax/Pr)(Tmin/Treq)2 + bdE + c Processor Energy Mean Deviation PACS2000

11. Experiments: EonE vs. S&S • hundred random graphs (20 nodes) • max four processors (four supply voltages) 50 40 30 20 Energy saved by EonE vs. S&S in % 10 0 -10 deadline extension in % 0 25 50 75 100 EonE gets in average ~15% lower energy PACS2000

12. Single Vdd EonE S&S 100 Energy consumption 50 0 Processors 2 3 4 2 3 4 Rate 6.25 Hz 8.33Hz Experiments: OFD • 32 tasks on DSPs with four Vdd • 12.5Hz, 78x120 pixels • >50% energy at half rate (6.25Hz) • higher parallelism allows lower energy consumption PACS2000

13. Conclusions • Two design approaches for low-energy systems containing variable Vdd processors • Speed-up and Stretch (simple, but efficient) • Eye-on-Energy (most efficient) • Schedule-driven assignment (using SA) • Experiments: • up to 50% energy savings for 50% deadline extension • performance vs. low-energy trade-off • cost (processor number) vs. low-energy trade-off PACS2000