Low Power Processors

1. Low Power Processors Josh Nanni Matt Rosonke Matt Tannenbaum

2. Power vs. Energy • Power is dissipation of energy over time • A device consuming lots of power over a long period of time will dissipate lots of heat • A device using lots of energy decreases the battery life 2 [Brehob]

3. Why Do We Care? About Power: • High power draws for extended periods of time can produce a lot of heat • Lots of heat can • melt components • cause faulty behavior • harm the user About Energy • High energy consumption will decrease battery life • Good battery life will increase portability 3

4. What Can I Power? 2 AA batteries can power a cheap calculator for several years [1] My House [2] "An Analysis of Power Consumption in a Smartphone". Aaron Carroll, Gernot Heiser. NICTA, University of New South Wales, Open Kernel Labs [3] http://en.wikipedia.org/wiki/Watt#Multiples 4 1

5. Challenge in Industry • Increase functionality, decrease power consumption • Performance increases -> increase power • Nvidia Tegra (Kal-El) • University of Michigan's Phoenix processor 5

6. Nvidia Kal-El • Nvidia Kal-El, also known as the Tegra processor is a quad core system on a chip developed for mobile applications • Multicores excel inachieving betterpower toperformance than single cores [C] 6

7. Background Processes • Kal El runs a companion core that runs background processes at low frequency and power • Extends battery life! [E] 7

8. Nvidia Kal-El • Main cores (fast ARMCoretex A9s) are enabled one by one for highperformance applications • Core switchinginvisible to apps • Disabling coreswhen not neededsaves energy [E] 8

9. Nvidia Kal-El • Designated cores for media processing can also be disabled when not needed to save power • Each media core is designed to do only one task as efficiently as possible [E] 9

10. EECS 312 Mumble Mumble.... • How does a slower core save power? • Narrower Gates = • Less gate capacitance • Lower saturation current • Architects make atrade off between thetwo to achieve the clock speed andpower consumptiondesired from the device [Sylvester] 10

11. EECS 370 Mumble Mumble... • Stage Skip Pipeline • Used during loops to skip instruction fetched and decodes by using a Decoded Instruction Buffer (DIB) [B] 11

12. EECS 370 Mumble Mumble... • Collapsable Pipelines • High performance = shorter stages, faster clock • Lower power = longer stages, slower clock [A] 12

13. Nvidia Kal-El Power / Performance • Companion Core - Low Leakage Current • Main Cores - Higher Leakage Current, Power Gated • Cores switch at optimal time [E] 13

14. Phoenix: a 30 pW Processor • Developed by PhD students at University of Michigan as an embedded systems processor specializing in extremely low standby power • Mingoo Seok, Scott Hanson, Yu-Shiang Lin, Zhiyoong Lee, Nurrachman Liu, with Dennis Sylvester and David Blaauw • Goal was to build a very small processor with a very long battery life • Relies on aggressive power gatingto minimize sleep power [h] 14

15. Phoenix: a 30 pW Processor • Phoenix uses ~300nW in active mode and 29.6 pW in sleep mode • Meant for embedded systems that spend most of their time in sleep mode • ~20ms of active time vs. 10 minutes of sleep time [MS Paint] [h] 15

16. Power Gating • Essentially, you use a transistor as a switch, cutting off sections you aren't using • Sizing is very important to consider.... [j] 16

17. So what can you power gate? • Can power gate: • ROM • Arithmetic units • Logic units • Non-volatile RAM • Cannot power gate: • Volatile RAM • Timers • Anything that needs to preserve state [h] 17

18. Situational Awareness • Certain processors are better for some systems than for others • You would never put this in a phone! • Note that as you deal with very low power, weird things become important • In Phoenix, instruction ROM is used to supplement now dominant instruction memory [h] 18

19. Questions? 19

20. References (1) • [A]"Stage-Skip pipeline: A Low Power Processor Architecture Using a Decoded Instruction Buffer". 1996. Mitsuri Hiraki, Raminder S. Bajwa, Hirotsuga Kojima, Douglas J. Gorny, Ken-ichi Nitta, Avadhani Shridhar, Katsuro Sasaki, Koichi Seki. • [B]"A Low-Power Processor Architecture Optimized for Wireless Devices". 2005. Aristides Efthymiou, Jim D. Garside, Ioannis Papaefstathiou. • [C]“The New Era of Tera-Scale Computing” 2009, Shu-ling Garver, Bob Crepps. • [D] “The Benefits of Quad Core CPUs in Mobile Devices” Nvidia 2011 http://www.nvidia.com/content/PDF/tegra_white_papers/tegra-whitepaper-0911a.pdf • [E]“Variable SMP –A Multi-Core CPU Architecture for Low Power and High Performance” Nvidia 2011http://www.nvidia.com/content/PDF/tegra_white_papers/tegra-whitepaper-0911b.pdf 21

21. References (2) Phoenix Processor: • [h] "The Phoenix Processor: A 30pW Platform for Sensor Applications". 2008. Mingoo Seok, Scott Hanson, Yu-Shiang Lin, Zhiyoong Lee, Nurrachman Liu, Dennis Sylvester, David Blaauw • [j] "A Low-Voltage Processor for Sensing Applications With Picowatt Standby Mode". 2009. Scott Hanson, Mingoo Seok, Yu-Shiang Lin, Zhiyoong Lee, Nurrachman Liu, Dennis Sylvester, David Blaauw Power Gating: • [k] "Power Gating Implementation in SoCs". Charwak Apte. http://nanocad.ee.ucla.edu/pub/Main/SnippetTutorial/PG.pdf 22