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High performance field programmable gate array for gigahertz applications. Jong-Ru Guo, C. You, M. Chu, K. Zhou, Jin-Woo Kim, B.S. Goda*, R.P. Kraft, J.F. McDonald Rensselaer Polytechnic Institute, Troy, NY, 12180 * United State Military Academy, West Point, N.Y. 10096. Gigahertz era.
Jong-Ru Guo, C. You, M. Chu, K. Zhou, Jin-Woo Kim, B.S. Goda*, R.P. Kraft, J.F. McDonald
Rensselaer Polytechnic Institute, Troy, NY, 12180
* United State Military Academy, West Point, N.Y. 10096
High speed reconfigurable system is needed to handle the increasing amount of data.
However, the CMOS FPGA just is operated at the hundreds MHz.
GHz reconfigurable system is needed.
A reconfigurable chip that can be
programmed for a specific function.
There are no FPGA’s that operate at
GHz microprocessor clock rates much
less at K-band or X-band.
Change this situation for the better.
Approximated cut-off frequency:
IBM 0.5 & 0.25 um generations (5HP)
~ 50 GHz
IBM 0.18 um generation (7HP)
~ 120 GHz
IBM 0.13 um generation (8HP)
~ 180 GHz
Observe the Logarithmic Ic Axis
Ref. 40-Gb/s Circuits Built From a 120-GHz fT SiGe Technology
IEEE Journal of Solid-State Circuit. VOL. 37, NO.9, Sept. 2003
SiGe Graded Base Bipolar Transistor
Ref. Flash Comm
Si/SiGe band diagram
Ref. Yuan Taur and Tak H. Ning “Fundamentals of Modern
VLSI Devices”, Cambridge University Press, p364, 1998.
LatchNew Structure: Input and Output Block and Function Unit (FU)
Function Unit (FU)
Schematic of the new function unit
Based on XC6200
(170um x 210um)
Propagation delay and power consumption comparisons between different processes
Measurement result of the 7HP ring oscillator
Measurement result of the 5HP Basic Cell
Power-saving scheme Usage 
Case I: Only combinational logic or sequential logic is used.
Case II: Sequential logic and redirection function are used.
Case III: Only redirection function is used.
With the latest Basic Cell, there will be 48x48 Basic Cell array in 7mm x 7mm area.
Propagation delay has been reduced by 82.5%
Power consumption has been reduced by 80.6% (5HP case and 8HP power saving case) for the fully turned-on case.
There is 94% power saved when the power-saving scheme is enabled.Summary: Basic Cell
Interleaving data path
High speed inputs
High speed front end
De-interleaving data path
To processors or other circuits
High speed outputs
High speed back end
DSP and other applications
Such as, Poly-phase filter, digital filter…etc
500MHz ~ 10GHz
10GHz ~ 80GHzHigh speed reconfigurable system
¼ CLK out
The block diagram of the 4:1 MUX
The building blocks of the 1:4 DEMUX.
CH1 CH2 CH3 CH4
1:4 DEMUX input
CH1 CH3 CH2 CH4
The timing diagram of the 4:1 MUX (x represents 1, 2, 3 and 4)
The timing diagram of the 1:4 DEMUX
High speed data acquisition MUX-DEMUX
Simulation results show both 4:1 MUX and
1:4 DEMUX can operate up to 10GHz
Compare to CMOS FPGA (Xilinx Virtex),
same circuits can run to 183MHz
Layout of the 4:1 MUX
Layout of the 1:4 DEMUX
Simulation result of the 4:1 MUX.
Inputs: CH_A: 1010011, CH_B: 0010100,
CH_C: 0101001 and CH_D: 0001010.
Simulated eye diagram of the 4:1 MUX programmed by SiGe FPGA runs at 10Gbps
Virtex results are based on the following environments:
Software: Foundation 2.1
Xilinx power consumption work sheet V1.5
with the dimension of 7mm x 7mm. (400 Basic Cells).
The layout has been reduced by 49% between the 8HP and 5HP generations.
Applications have been proposed to run at GHz range.
4:1 MUX and 1:4 DEMUX have been configured to compare the performance of SiGe and CMOS FPGA.Conclusion
Primitive layout of the 48x48 SiGe FPGA